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Fix LZCN, NZCN, R3CN EC offsets.#433

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MrDuartePT merged 1 commit into
johnfanv2:mainfrom
qquique:loq-ec-offsets
May 7, 2026
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Fix LZCN, NZCN, R3CN EC offsets.#433
MrDuartePT merged 1 commit into
johnfanv2:mainfrom
qquique:loq-ec-offsets

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@qquique

@qquique qquique commented May 7, 2026

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  • Adds R3CN ec offsets and model.
  • Adds acpi paths for those models.
  • Enable extreme powermode for those models.
  • Allows modification of Point 1.
  • Can modify RPM/Temps on Custom mode with CMDR bit.
Details 
This memory area from 0xc400 + 0x100-> shows: 
cpu (min T, max T, rpm)
gpu (min T, max T, rpm)
changes to them has no effect. So we use them as readonly.

LZCN
00000000  00 01 00 00 00 00 00 01  01 40 80 70 00 a6 5c 00  |.........@.p..\.|
00000010  00 00 26 23 26 28 28 27  02 c9 00 00 40 62 00 42  |..&#&(('....@b.B|
00000020  aa 00 00 00 00 00 00 00  00 00 00 00 00 00 00 00  |................|
00000030  00 00 00 00 00 00 00 00  00 00 00 00 00 00 00 00  |................|
*
00000060  00 80 16 17 bc 00 00 00  00 00 00 00 00 00 00 00  |................|
00000070  00 00 00 00 00 00 00 00  00 00 00 00 00 00 00 00  |................|
00000080  00 00 00 00 02 00 00 00  00 00 00 00 00 00 00 00  |................|
00000090  00 00 00 00 00 00 00 00  00 00 00 00 00 00 00 00  |................|
000000a0  00 00 00 c8 40 00 00 2e  23 00 00 08 00 2a 00 78  |....@...#....*.x|
000000b0  2e 2e 00 00 23 00 00 00  00 00 00 0f 00 6a 00 00  |....#........j..|
000000c0  00 02 83 14 30 08 80 40  50 3c 70 17 b7 15 5e 1c  |....0..@P<p...^.|
000000d0  00 00 00 00 00 00 b7 15  2b 02 59 01 00 00 12 57  |........+.Y....W|
000000e0  00 00 00 20 10 20 10 20  10 20 10 00 00 00 00 00  |... . . . ......|
000000f0  00 00 00 00 00 00 a0 41  45 00 00 ff ff 00 00 00  |.......AE.......|
00000100  00 00 00 03 00 0a 05 00  54 00 3c 54 23 50 5c 23  |........T.<T#P\#|
00000110  50 5c 23 50 5c 23 50 5c  23 50 5c 23 50 5c 23 52  |P\#P\#P\#P\#P\#R|
00000120  63 23 5e 64 23 00 00 00  00 00 03 00 0a 00 00 54  |c#^d#..........T|
00000130  00 3c 54 23 50 5c 23 50  5c 23 50 5c 23 50 5c 23  |.<T#P\#P\#P\#P\#|
00000140  50 5c 23 50 5c 23 52 63  23 5e 64 23 00 00 00 00  |P\#P\#Rc#^d#....|
00000150  00 00 00 00 00 00 00 00  00 00 00 00 00 00 00 00  |................|
*
000001a0  08 00 00 00 00 00 00 00  00 00 00 00 00 00 00 00  |................|
000001b0  00 00 00 00 00 00 00 00  00 00 00 00 00 00 00 00  |................|
*
00000200  01 01 01 01 00 00 11 00  00 00 00 00 00 00 00 00  |................|
00000210  02 0c 0e 11 15 15 15 15  15 2a 00 00 00 00 00 00  |.........*......|
00000220  5a a5 00 00 00 00 00 00  00 00 00 45 c1 00 00 00  |Z..........E....|
00000230  00 00 00 00 00 00 00 00  00 00 00 00 00 00 00 00  |................|
00000240  01 23 00 00 00 00 00 00  00 00 00 00 00 00 00 00  |.#..............|
00000250  00 00 00 00 00 00 00 00  00 00 00 00 00 00 00 00  |................|

Powermode : 0xc400 + 10 = 0xc40a, 3 bits
Cpu Fan base : 0xc400 + 0x100 + 9   = 0xc509
Cpu Max Temp Base : 0xc400 + 0x100 + 8   = 0xc508
Cpu Min Temp Base : 0xc400 + 0x100 + 7   = 0xc507

Gpu Fan base : 0xc400 + 0x130       = 0xc530
Gpu Max Temp base : 0xc400 + 0x120 + 15  = 0xc52f
Gpu Min Temp base : 0xc400 + 0x120 + 14  = 0xc52e

OperationRegion (EFAN, SystemMemory, 0xFE0B0F00, 0x1000)


NZCN
00000000  00 00 00 80 00 00 00 09  01 00 90 60 00 2e 5c 00  |...........`..\.|
00000010  00 00 27 28 2a 29 29 00  20 20 03 0c 40 62 00 20  |..'(*)).  ..@b. |
00000020  aa 00 00 00 00 00 00 00  00 00 00 00 00 00 00 00  |................|
00000030  00 00 00 00 00 00 00 00  00 00 00 00 00 00 00 00  |................|
*
00000060  00 80 16 17 08 00 00 00  00 00 00 00 00 00 00 00  |................|
00000070  00 00 00 00 00 00 00 00  00 00 00 00 00 00 00 00  |................|
00000080  00 00 00 00 02 00 00 00  00 00 00 00 00 00 00 00  |................|
00000090  28 00 00 00 00 00 00 00  00 00 00 00 00 00 00 00  |(...............|
000000a0  00 00 04 c8 40 00 c0 00  2a 00 00 08 00 2a 00 00  |....@...*....*..|
000000b0  00 28 00 00 2b 00 00 00  00 00 00 0f 00 72 00 00  |.(..+........r..|
000000c0  00 08 ef 12 16 04 12 3b  50 3c 70 17 13 18 4f 1f  |.......;P<p...O.|
000000d0  00 00 00 00 38 12 13 18  68 02 59 11 00 04 91 59  |....8...h.Y....Y|
000000e0  00 00 00 c3 0e c3 0e c7  0e c6 0e 00 00 00 00 00  |................|
000000f0  00 00 00 00 00 00 30 43  06 0d 00 ff ff 00 00 00  |......0C........|
00000100  01 65 14 91 0e 0f 05 00  46 00 3c 49 0e 46 4d 11  |.e......F.<I.FM.|
00000110  4b 50 13 4e 54 16 50 54  19 52 5c 1f 57 5f 23 5c  |KP.NT.PT.R\.W_#\|
00000120  63 30 5e 64 30 0e 0e 01  65 14 91 0e 0f 00 00 46  |c0^d0...e......F|
00000130  00 3c 49 0e 46 4d 11 4b  50 13 4e 54 16 50 54 19  |.<I.FM.KP.NT.PT.|
00000140  52 5c 1f 57 5f 23 5c 63  30 5e 64 30 0e 0e 00 00  |R\.W_#\c0^d0....|
00000150  00 00 00 00 00 00 00 00  00 00 00 00 00 00 00 00  |................|
*

Powermode : 0xc400 + 10 = 0xc40a, 3 bits
Cpu Fan base : 0xc400 + 0x100 + 9   = 0xc509
Cpu Max Temp Base : 0xc400 + 0x100 + 8   = 0xc508
Cpu Min Temp Base : 0xc400 + 0x100 + 7   = 0xc507

Gpu Fan base : 0xc400 + 0x130       = 0xc530
Gpu Max Temp base : 0xc400 + 0x120 + 15  = 0xc52f
Gpu Min Temp base : 0xc400 + 0x120 + 14  = 0xc52e

OperationRegion (EFAN, SystemMemory, 0xFE0B0F00, 0x1000)

R3CN
00000000  00 00 00 00 00 00 00 09  01 00 90 00 00 2f 5c 00  |............./\.|
00000010  00 00 00 00 00 00 00 00  22 30 02 08 40 62 00 02  |........"0..@b..|
00000020  e6 00 00 00 00 00 00 00  00 00 00 00 00 00 00 00  |................|
00000030  00 00 00 00 00 00 00 00  00 00 00 00 00 00 00 00  |................|
*
00000060  00 80 16 52 21 0a 00 00  00 00 00 00 00 00 00 00  |...R!...........|
00000070  00 00 00 00 00 00 00 00  00 00 00 00 00 00 00 00  |................|
00000080  00 00 00 00 02 00 00 00  00 00 00 00 00 00 00 00  |................|
00000090  00 31 2b 2b 00 00 30 00  00 00 00 00 00 00 00 00  |.1++..0.........|
000000a0  01 00 00 c0 40 00 00 30  2c 00 00 08 00 2e 00 78  |....@..0,......x|
000000b0  30 30 29 00 2c 00 32 2c  00 00 00 0f 00 42 50 5b  |00).,.2,.....BP[|
000000c0  0a 00 00 00 00 00 00 00  00 00 00 00 00 00 00 00  |................|
000000d0  00 00 00 00 00 00 00 00  00 00 00 00 00 00 00 00  |................|
*
000000f0  00 00 00 00 00 00 00 00  00 00 00 ff ff 00 00 00  |................|
00000100  02 65 1c db 10 19 05 00  32 00 28 36 0b 32 3a 10  |.e......2.(6.2:.|
00000110  36 3e 11 3a 42 13 3e 46  15 42 4a 18 46 4e 1c 4a  |6>.:B.>F.BJ.FN.J|
00000120  52 1e 4a 52 21 4a 52 21  4a 52 21 4a 63 21 4a 64  |R.JR!JR!JR!Jc!Jd|
00000130  21 10 10 02 65 1d d1 11  13 00 00 32 00 28 36 0e  |!...e......2.(6.|
00000140  32 3a 11 36 3e 14 3a 42  16 3e 46 18 42 4a 1b 46  |2:.6>.:B.>F.BJ.F|
00000150  4e 1f 4a 52 21 4a 52 24  4a 52 24 4a 52 24 4a 63  |N.JR!JR$JR$JR$Jc|
00000160  24 4a 64 24 11 11 00 00  00 00 00 00 00 00 00 00  |$Jd$............|
00000170  00 00 00 00 00 00 00 00  00 00 00 00 00 00 00 00  |................|

Powermode : 0xc400 + 10 = 0xc40a, 3 bits
Cpu Fan base : 0xc400 + 0x100 + 9   = 0xc509
Cpu Max Temp Base : 0xc400 + 0x100 + 8   = 0xc508
Cpu Min Temp Base : 0xc400 + 0x100 + 7   = 0xc507

Gpu Fan base : 0xc400 + 0x130 + 12  = 0xc53c
Gpu Max Temp base : 0xc400 + 0x130 + 11  = 0xc53b
Gpu Min Temp base : 0xc400 + 0x130 + 10  = 0xc53a

OperationRegion (EFAN, SystemMemory, 0xFE0B0F00, 0x1000)


The SystemMemory Address 0xFE0B0F00 has same offsets for 
cpu(min T,max T, rpm), 
gpu(min T, max T, rpm), 
ic (min T, max T, rpm) 

For the laptop models, this area starts with 0 values and it starts populating when methods 
SFAN, GFAN, SFA2 are called or VantageApp is used, in Custom mode, with values from default fan/temp tables.

| LZCN          | NZCN          | R3CN          |
| ------------- | ------------- | ------------- |
| CL00          | CL00          | CL00          |
| CT00          | CT00          | CT00          |
| CRP0          | CRP0          | CRP0          |
| Offset (0x06) | Offset (0x06) | Offset (0x06) |
| CL01          | CL01          | CL01          |
| CT01          | CT01          | CT01          |
| CRP1          | CRP1          | CRP1          |
| Offset (0x0C) | Offset (0x0C) | Offset (0x0C) |
| CL02          | CL02          | CL02          |
| CT02          | CT02          | CT02          |
| CRP2          | CRP2          | CRP2          |
| Offset (0x12) | Offset (0x12) | Offset (0x12) |
| CL03          | CL03          | CL03          |
| CT03          | CT03          | CT03          |
| CRP3          | CRP3          | CRP3          |
| Offset (0x18) | Offset (0x18) | Offset (0x18) |
| CL04          | CL04          | CL04          |
| CT04          | CT04          | CT04          |
| CRP4          | CRP4          | CRP4          |
| Offset (0x1E) | Offset (0x1E) | Offset (0x1E) |
| CL05          | CL05          | CL05          |
| CT05          | CT05          | CT05          |
| CRP5          | CRP5          | CRP5          |
| Offset (0x24) | Offset (0x24) | Offset (0x24) |
| CL06          | CL06          | CL06          |
| CT06          | CT06          | CT06          |
| CRP6          | CRP6          | CRP6          |
| Offset (0x2A) | Offset (0x2A) | Offset (0x2A) |
| CL07          | CL07          | CL07          |
| CT07          | CT07          | CT07          |
| CRP7          | CRP7          | CRP7          |
| Offset (0x30) | Offset (0x30) | Offset (0x30) |
| CL08          | CL08          | CL08          |
| CT08          | CT08          | CT08          |
| CRP8          | CRP8          | CRP8          |
| Offset (0x34) | Offset (0x34) | Offset (0x34) |
| CRA8          | CRA8          | CRA8          |
| CL09          | CL09          | CL09          |
| CT09          | CT09          | CT09          |
| CRP9          | CRP9          | CRP9          |
| Offset (0x3B) | Offset (0x3B) | Offset (0x3B) |
| CTA9          | CTA9          | CTA9          |
| GL00          | GL00          | GL00          |
| GT00          | GT00          | GT00          |
| GRP0          | GRP0          | GRP0          |
| Offset (0x42) | Offset (0x42) | Offset (0x42) |
| GL01          | GL01          | GL01          |
| GT01          | GT01          | GT01          |
| GRP1          | GRP1          | GRP1          |
| Offset (0x48) | Offset (0x48) | Offset (0x48) |
| GL02          | GL02          | GL02          |
| GT02          | GT02          | GT02          |
| GRP2          | GRP2          | GRP2          |
| Offset (0x4E) | Offset (0x4E) | Offset (0x4E) |
| GL03          | GL03          | GL03          |
| GT03          | GT03          | GT03          |
| GRP3          | GRP3          | GRP3          |
| Offset (0x54) | Offset (0x54) | Offset (0x54) |
| GL04          | GL04          | GL04          |
| GT04          | GT04          | GT04          |
| GRP4          | GRP4          | GRP4          |
| Offset (0x5A) | Offset (0x5A) | Offset (0x5A) |
| GL05          | GL05          | GL05          |
| GT05          | GT05          | GT05          |
| GRP5          | GRP5          | GRP5          |
| Offset (0x60) | Offset (0x60) | Offset (0x60) |
| GL06          | GL06          | GL06          |
| GT06          | GT06          | GT06          |
| GRP6          | GRP6          | GRP6          |
| Offset (0x66) | Offset (0x66) | Offset (0x66) |
| GL07          | GL07          | GL07          |
| GT07          | GT07          | GT07          |
| GRP7          | GRP7          | GRP7          |
| Offset (0x6C) | Offset (0x6C) | Offset (0x6C) |
| GL08          | GL08          | GL08          |
| GT08          | GT08          | GT08          |
| GRP8          | GRP8          | GRP8          |
| Offset (0x70) | Offset (0x70) | Offset (0x70) |
| GRA8          | GRA8          | GRA8          |
| Offset (0x72) | Offset (0x72) | Offset (0x72) |
| GL09          | GL09          | GL09          |
| GT09          | GT09          | GT09          |
| GRP9          | GRP9          | GRP9          |
| Offset (0x77) | Offset (0x77) | Offset (0x77) |
| GTA9          | GTA9          | GTA9          |
| EL00          | EL00          | EL00          |
| ET00          | ET00          | ET00          |
| ERP0          | ERP0          | ERP0          |
| Offset (0x7E) | Offset (0x7E) | Offset (0x7E) |
| EL01          | EL01          | EL01          |
| ET01          | ET01          | ET01          |
| ERP1          | ERP1          | ERP1          |
| Offset (0x84) | Offset (0x84) | Offset (0x84) |
| EL02          | EL02          | EL02          |
| ET02          | ET02          | ET02          |
| ERP2          | ERP2          | ERP2          |
| Offset (0x8A) | Offset (0x8A) | Offset (0x8A) |
| EL03          | EL03          | EL03          |
| ET03          | ET03          | ET03          |
| ERP3          | ERP3          | ERP3          |
| Offset (0x90) | Offset (0x90) | Offset (0x90) |
| EL04          | EL04          | EL04          |
| ET04          | ET04          | ET04          |
| ERP4          | ERP4          | ERP4          |
| Offset (0x96) | Offset (0x96) | Offset (0x96) |
| EL05          | EL05          | EL05          |
| ET05          | ET05          | ET05          |
| ERP5          | ERP5          | ERP5          |
| Offset (0x9C) | Offset (0x9C) | Offset (0x9C) |
| EL06          | EL06          | EL06          |
| ET06          | ET06          | ET06          |
| ERP6          | ERP6          | ERP6          |
| Offset (0xA2) | Offset (0xA2) | Offset (0xA2) |
| EL07          | EL07          | EL07          |
| ET07          | ET07          | ET07          |
| ERP7          | ERP7          | ERP7          |
| Offset (0xA8) | Offset (0xA8) | Offset (0xA8) |
| EL08          | EL08          | EL08          |
| ET08          | ET08          | ET08          |
| ERP8          | ERP8          | ERP8          |
| Offset (0xAC) | Offset (0xAC) | Offset (0xAC) |
| ERA8          | ERA8          | ERA8          |
| Offset (0xAE) | Offset (0xAE) | Offset (0xAE) |
| EL09          | EL09          | EL09          |
| ET09          | ET09          | ET09          |
| ERP9          | ERP9          | ERP9          |

And starts at 0xc400 + 0xb00 = 0xcf00 for those models.

Fan 1 RPM Base = 0xcf00 + 2             = 0xcf02
Fan 1 Max Temp Base = 0xcf00 + 1        = 0xcf01
Fan 1 Min Temp Base = 0xcf00            = 0xcf00

Fan 2 RPM Base = 0xcf00 + 0x3b + 3      = 0xcf3e
Fan 2 Max Temp Base = 0xcf00 + 0x3b + 2 = 0xcf3d
Fan 2 Max Temp Base = 0xcf00 + 0x3b + 1 = 0xcf3c

IC Min Temp Base = 0xcf00 + 0x77 + 1    = 0xcf78
IC Max Temp Base = 0xcf00 + 0x77 + 2    = 0xcf79

after modifying needs to set bit CMRD to 1 to execute as SFAN does
Offset : 0xcf00 + 0xb3 + 3 = 0xcfb6

@qquique
Fix LZCN, NZCN, R3CN EC offsets.
5036fbd 
- Adds R3CN ec offsets and model.
- Adds acpi paths for those models.
- Enable extreme powermode for those models.
- Allows modification of Point 1.
- Can modify RPM/Temps on Custom mode with CMDR bit.
@MrDuartePT

MrDuartePT commented May 7, 2026 •
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Everything with the code looks fine!
Thanks for adding LOQ support!

@MrDuartePT MrDuartePT merged commit 914c1a3 into johnfanv2:main May 7, 2026
6 of 7 checks passed
@qquique qquique deleted the loq-ec-offsets branch May 12, 2026 04:20
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2 participants

@qquique @MrDuartePT