Update Ghidra HEAD to commit f9e13846b

[auto-updater]

Changed files:

M	Ghidra/Features/Decompiler/src/decompile/cpp/architecture.cc
M	Ghidra/Features/Decompiler/src/decompile/cpp/architecture.hh
M	Ghidra/Features/Decompiler/src/decompile/cpp/flow.cc
M	Ghidra/Features/Decompiler/src/decompile/cpp/flow.hh
M	Ghidra/Features/Decompiler/src/decompile/cpp/funcdata_op.cc
M	Ghidra/Features/Decompiler/src/decompile/cpp/marshal.cc
M	Ghidra/Features/Decompiler/src/decompile/cpp/options.cc
M	Ghidra/Features/Decompiler/src/decompile/cpp/options.hh
M	Ghidra/Processors/ARM/data/languages/ARMTHUMBinstructions.sinc
M	Ghidra/Processors/SuperH/certification.manifest
M	Ghidra/Processors/SuperH/data/languages/superh.ldefs
A	Ghidra/Processors/SuperH/data/manuals/superh.idx
M	Ghidra/Processors/tricore/data/languages/tricore.sinc

Commit details:

[Commit 1/6]
Hash: 4170459fddba20856f22dc839421cd5e7473e78d
Date: 2026-06-16 14:01:12 +0000
Message: GP-6964: Added index entries for 1dc/lds/stc/sts.l instructions

Files changed:
  M	Ghidra/Processors/SuperH/data/manuals/superh.idx

[Commit 2/6]
Hash: 333674114e50c11c82096d6ad0870d2eed8b8278
Date: 2026-06-15 11:02:21 -0400
Message: GP-6769: Corrected tricore carry flag calculations

Files changed:
  M	Ghidra/Processors/tricore/data/languages/tricore.sinc

[Commit 3/6]
Hash: 82c4d30b385e5174d81361d822e1d57c1a7b2834
Date: 2026-06-15 14:45:06 +0000
Message: GP-6964: Added index file to SH2-A language variant

Files changed:
  M	Ghidra/Processors/SuperH/certification.manifest
  M	Ghidra/Processors/SuperH/data/languages/superh.ldefs

[Commit 4/6]
Hash: 4f593bd8d4dbfa3ef16018acd72d564ec7d65477
Date: 2026-06-14 18:29:48 -0500
Message: Added SH-1 and SH-2 manual name and index

Files changed:
  M	Ghidra/Processors/SuperH/data/languages/superh.ldefs
  A	Ghidra/Processors/SuperH/data/manuals/superh.idx

[Commit 5/6]
Hash: d424b6ff9bc06d9d954ac49cf83098fff04d9092
Date: 2026-03-31 22:24:22 +0000
Message: GP-6945 Count bad data exceptions

Files changed:
  M	Ghidra/Features/Decompiler/src/decompile/cpp/architecture.cc
  M	Ghidra/Features/Decompiler/src/decompile/cpp/architecture.hh
  M	Ghidra/Features/Decompiler/src/decompile/cpp/flow.cc
  M	Ghidra/Features/Decompiler/src/decompile/cpp/flow.hh
  M	Ghidra/Features/Decompiler/src/decompile/cpp/funcdata_op.cc
  M	Ghidra/Features/Decompiler/src/decompile/cpp/marshal.cc
  M	Ghidra/Features/Decompiler/src/decompile/cpp/options.cc
  M	Ghidra/Features/Decompiler/src/decompile/cpp/options.hh

[Commit 6/6]
Hash: 1de7de83e4e1987f46d9e4fce0ab45e1e17c907a
Date: 2024-05-29 23:19:58 -0700
Message: Fix input register for msr apsr
Details:
The msr instruction get the output register from the second 16-bit word,
but it must come out of the first 16-bit word.

This patch fixes the decoding.

Files changed:
  M	Ghidra/Processors/ARM/data/languages/ARMTHUMBinstructions.sinc