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1. UART-Tx-Rx-Basys3 UART-Tx-Rx-Basys3 Public

   This project demonstrates the design and implementation of a UART (Universal Asynchronous Receiver-Transmitter) module—both RX and TX—on the Basys 3 FPGA development board using Verilog. The design…

   Tcl 1

2. Asynchronous-FIFO Asynchronous-FIFO Public

   Asynchronous FIFO implementation using verilog.

   Verilog

3. SoC_design_and_planning_digital_vlsi SoC_design_and_planning_digital_vlsi Public

   Documentation of the work done during the 2 weeks workshop on SoC design and Planning and ASIC backend flow in OpenLane.

4. Single_Cycle_RISC-V Single_Cycle_RISC-V Public

   Verilog

5. Robosoc_3D_printer Robosoc_3D_printer Public

   Documentation of the project 3D-Printer based on Arduino Mega and Ramps 1.4.

   C++ 2

6. HDL_bits_Verilog_Solutions HDL_bits_Verilog_Solutions Public

   Solutions of Verilog problems listed on HDL bits in a systematic manner.

   Verilog