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virt: move SynicPorts to virt crate and decouple from CpuIo #3217

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Merged
jstarks merged 5 commits into from
Apr 7, 2026
Merged

virt: move SynicPorts to virt crate and decouple from CpuIo #3217

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virt: move SynicPorts to virt crate and decouple from CpuIo
jstarks Apr 7, 2026
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fix: apply rustfmt formatting fixes
jstarks Apr 7, 2026
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jstarks Apr 7, 2026
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4 changes: 2 additions & 2 deletions openhcl/underhill_core/src/vp.rs
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Original file line number Diff line number Diff line change
Expand Up @@ -16,7 +16,7 @@ pub(crate) async fn spawn_vps(
tp: &AffinitizedThreadpool,
vps: Vec<virt_mshv_vtl::UhProcessorBox>,
runners: Vec<vmm_core::partition_unit::VpRunner>,
chipset: &vmm_core::vmotherboard_adapter::ChipsetPlusSynic,
chipset: &vmm_core::vmotherboard_adapter::AdaptedChipset,
isolation: virt::IsolationType,
) -> anyhow::Result<()> {
// Start the VP tasks on the thread pool.
Expand Down Expand Up @@ -46,7 +46,7 @@ pub(crate) async fn spawn_vps(
struct VpSpawner {
vp: virt_mshv_vtl::UhProcessorBox,
cpu: u32,
chipset: vmm_core::vmotherboard_adapter::ChipsetPlusSynic,
chipset: vmm_core::vmotherboard_adapter::AdaptedChipset,
runner: vmm_core::partition_unit::VpRunner,
isolation: virt::IsolationType,
tp: AffinitizedThreadpool,
Expand Down
9 changes: 2 additions & 7 deletions openhcl/underhill_core/src/worker.rs
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Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -175,7 +175,6 @@ use vmm_core::input_distributor::InputDistributor;
use vmm_core::partition_unit::Halt;
use vmm_core::partition_unit::PartitionUnit;
use vmm_core::partition_unit::PartitionUnitParams;
use vmm_core::synic::SynicPorts;
use vmm_core::vmbus_unit::ChannelUnit;
use vmm_core::vmbus_unit::VmbusServerHandle;
use vmm_core::vmbus_unit::offer_channel_unit;
Expand Down Expand Up @@ -2672,7 +2671,7 @@ async fn new_underhill_vm(

let emuplat_adjust_gpa_range;

let synic = Arc::new(SynicPorts::new(partition.clone()));
let synic = virt::Hv1::synic(partition.clone());

let mut chipset = vm_manifest_builder::VmManifestBuilder::new(
match firmware_type {
Expand Down Expand Up @@ -3552,11 +3551,7 @@ async fn new_underhill_vm(
block_on(wait_for_flush_logs(&control_send_clone));
}))
};
let chipset = vmm_core::vmotherboard_adapter::ChipsetPlusSynic::new(
synic.clone(),
chipset,
fatal_error_policy,
);
let chipset = vmm_core::vmotherboard_adapter::AdaptedChipset::new(chipset, fatal_error_policy);

if let Some(vpci_relay) = &mut vpci_relay {
// Relay the initial set of VPCI devices.
Expand Down
16 changes: 13 additions & 3 deletions openhcl/virt_mshv_vtl/src/lib.rs
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Original file line number Diff line number Diff line change
Expand Up @@ -242,6 +242,7 @@ struct UhPartitionInner {
#[inspect(hex, with = "|x| inspect::iter_by_index(x.read().into_inner())")]
device_vector_table: RwLock<IrrBitmap>,
vmbus_relay: bool,
synic_ports: virt::synic::SynicPortMap,
}

#[derive(Inspect)]
Expand Down Expand Up @@ -982,7 +983,11 @@ impl UhPartitionInner {
}
}

impl virt::Synic for UhPartition {
impl virt::synic::Synic for UhPartition {
fn port_map(&self) -> &virt::synic::SynicPortMap {
&self.inner.synic_ports
}

fn post_message(&self, vtl: Vtl, vp_index: VpIndex, sint: u8, typ: u32, payload: &[u8]) {
let vtl = GuestVtl::try_from(vtl).expect("higher vtl not configured");
let Some(vp) = self.inner.vp(vp_index) else {
Expand Down Expand Up @@ -1024,12 +1029,12 @@ impl virt::Synic for UhPartition {
false
}

fn monitor_support(&self) -> Option<&dyn virt::SynicMonitor> {
fn monitor_support(&self) -> Option<&dyn virt::synic::SynicMonitor> {
Some(self)
}
}

impl virt::SynicMonitor for UhPartition {
impl virt::synic::SynicMonitor for UhPartition {
fn set_monitor_page(&self, vtl: Vtl, gpa: Option<u64>) -> anyhow::Result<()> {
// Keep this locked the whole function to avoid racing with allocate_monitor_page.
let mut allocated_block = self.inner.allocated_monitor_page.lock();
Expand Down Expand Up @@ -1275,6 +1280,10 @@ impl virt::Hv1 for UhPartition {
) -> Option<&dyn virt::DeviceBuilder<Device = Self::Device, Error = Self::Error>> {
self.inner.software_devices.is_some().then_some(self)
}

fn synic(self: Arc<Self>) -> Arc<dyn vmcore::synic::SynicPortAccess> {
Arc::new(virt::synic::SynicPorts::new(self))
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@smalis-msft smalis-msft Apr 7, 2026

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So this is an Arc, to a trait object, that contains just an Arc...

}
}

impl GetReferenceTime for UhPartitionInner {
Expand Down Expand Up @@ -1933,6 +1942,7 @@ impl<'a> UhProtoPartition<'a> {
device_vector_table: RwLock::new(IrrBitmap::new(Default::default())),
intercept_debug_exceptions: params.intercept_debug_exceptions,
vmbus_relay: late_params.vmbus_relay,
synic_ports: Default::default(),
});

if cfg!(guest_arch = "x86_64") {
Expand Down
64 changes: 32 additions & 32 deletions openhcl/virt_mshv_vtl/src/processor/hardware_cvm/mod.rs
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Original file line number Diff line number Diff line change
Expand Up @@ -123,7 +123,7 @@ impl Drop for RedirectedVectorMapping<'_> {
}
}

impl<T, B: HardwareIsolatedBacking> UhHypercallHandler<'_, '_, T, B> {
impl<B: HardwareIsolatedBacking> UhHypercallHandler<'_, '_, B> {
fn validate_register_access(
&mut self,
target_vtl: GuestVtl,
Expand Down Expand Up @@ -874,8 +874,8 @@ impl<T, B: HardwareIsolatedBacking> UhHypercallHandler<'_, '_, T, B> {
}
}

impl<T: CpuIo, B: HardwareIsolatedBacking> hv1_hypercall::ModifySparseGpaPageHostVisibility
for UhHypercallHandler<'_, '_, T, B>
impl<B: HardwareIsolatedBacking> hv1_hypercall::ModifySparseGpaPageHostVisibility
for UhHypercallHandler<'_, '_, B>
{
fn modify_gpa_visibility(
&mut self,
Expand Down Expand Up @@ -915,7 +915,7 @@ impl<T: CpuIo, B: HardwareIsolatedBacking> hv1_hypercall::ModifySparseGpaPageHos
}
}

impl<T: CpuIo, B: HardwareIsolatedBacking> UhHypercallHandler<'_, '_, T, B> {
impl<B: HardwareIsolatedBacking> UhHypercallHandler<'_, '_, B> {
fn retarget_physical_interrupt(
&mut self,
device_id: u64,
Expand Down Expand Up @@ -1083,8 +1083,8 @@ impl<T: CpuIo, B: HardwareIsolatedBacking> UhHypercallHandler<'_, '_, T, B> {
}
}

impl<T, B: HardwareIsolatedBacking> hv1_hypercall::GetVpRegisters
for UhHypercallHandler<'_, '_, T, B>
impl<B: HardwareIsolatedBacking> hv1_hypercall::GetVpRegisters
for UhHypercallHandler<'_, '_, B>
{
fn get_vp_registers(
&mut self,
Expand Down Expand Up @@ -1114,8 +1114,8 @@ impl<T, B: HardwareIsolatedBacking> hv1_hypercall::GetVpRegisters
}
}

impl<T: CpuIo, B: HardwareIsolatedBacking> hv1_hypercall::RetargetDeviceInterrupt
for UhHypercallHandler<'_, '_, T, B>
impl<B: HardwareIsolatedBacking> hv1_hypercall::RetargetDeviceInterrupt
for UhHypercallHandler<'_, '_, B>
{
fn retarget_interrupt(
&mut self,
Expand Down Expand Up @@ -1154,8 +1154,8 @@ impl<T: CpuIo, B: HardwareIsolatedBacking> hv1_hypercall::RetargetDeviceInterrup
}
}

impl<T, B: HardwareIsolatedBacking> hv1_hypercall::SetVpRegisters
for UhHypercallHandler<'_, '_, T, B>
impl<B: HardwareIsolatedBacking> hv1_hypercall::SetVpRegisters
for UhHypercallHandler<'_, '_, B>
{
fn set_vp_registers(
&mut self,
Expand Down Expand Up @@ -1184,7 +1184,7 @@ impl<T, B: HardwareIsolatedBacking> hv1_hypercall::SetVpRegisters
}
}

impl<T, B: HardwareIsolatedBacking> hv1_hypercall::VtlCall for UhHypercallHandler<'_, '_, T, B> {
impl<B: HardwareIsolatedBacking> hv1_hypercall::VtlCall for UhHypercallHandler<'_, '_, B> {
fn is_vtl_call_allowed(&self) -> bool {
// Only allowed from VTL 0
if self.intercepted_vtl != GuestVtl::Vtl0 {
Expand Down Expand Up @@ -1215,7 +1215,7 @@ impl<T, B: HardwareIsolatedBacking> hv1_hypercall::VtlCall for UhHypercallHandle
}
}

impl<T, B: HardwareIsolatedBacking> hv1_hypercall::VtlReturn for UhHypercallHandler<'_, '_, T, B> {
impl<B: HardwareIsolatedBacking> hv1_hypercall::VtlReturn for UhHypercallHandler<'_, '_, B> {
fn is_vtl_return_allowed(&self) -> bool {
if self.intercepted_vtl != GuestVtl::Vtl1 {
tracelimit::warn_ratelimited!(
Expand Down Expand Up @@ -1254,9 +1254,9 @@ impl<T, B: HardwareIsolatedBacking> hv1_hypercall::VtlReturn for UhHypercallHand
}
}

impl<T, B: HardwareIsolatedBacking>
impl<B: HardwareIsolatedBacking>
hv1_hypercall::StartVirtualProcessor<hvdef::hypercall::InitialVpContextX64>
for UhHypercallHandler<'_, '_, T, B>
for UhHypercallHandler<'_, '_, B>
{
fn start_virtual_processor(
&mut self,
Expand Down Expand Up @@ -1341,8 +1341,8 @@ impl<T, B: HardwareIsolatedBacking>
}
}

impl<T, B: HardwareIsolatedBacking> hv1_hypercall::ModifyVtlProtectionMask
for UhHypercallHandler<'_, '_, T, B>
impl<B: HardwareIsolatedBacking> hv1_hypercall::ModifyVtlProtectionMask
for UhHypercallHandler<'_, '_, B>
{
fn modify_vtl_protection_mask(
&mut self,
Expand Down Expand Up @@ -1399,8 +1399,8 @@ impl<T, B: HardwareIsolatedBacking> hv1_hypercall::ModifyVtlProtectionMask
}
}

impl<T: CpuIo, B: HardwareIsolatedBacking> hv1_hypercall::QuerySparseGpaPageHostVisibility
for UhHypercallHandler<'_, '_, T, B>
impl<B: HardwareIsolatedBacking> hv1_hypercall::QuerySparseGpaPageHostVisibility
for UhHypercallHandler<'_, '_, B>
{
fn query_gpa_visibility(
&mut self,
Expand All @@ -1423,8 +1423,8 @@ impl<T: CpuIo, B: HardwareIsolatedBacking> hv1_hypercall::QuerySparseGpaPageHost
}
}

impl<T, B: HardwareIsolatedBacking> hv1_hypercall::EnablePartitionVtl
for UhHypercallHandler<'_, '_, T, B>
impl<B: HardwareIsolatedBacking> hv1_hypercall::EnablePartitionVtl
for UhHypercallHandler<'_, '_, B>
{
fn enable_partition_vtl(
&mut self,
Expand Down Expand Up @@ -1485,9 +1485,9 @@ impl<T, B: HardwareIsolatedBacking> hv1_hypercall::EnablePartitionVtl
}
}

impl<T, B: HardwareIsolatedBacking>
impl<B: HardwareIsolatedBacking>
hv1_hypercall::EnableVpVtl<hvdef::hypercall::InitialVpContextX64>
for UhHypercallHandler<'_, '_, T, B>
for UhHypercallHandler<'_, '_, B>
{
fn enable_vp_vtl(
&mut self,
Expand Down Expand Up @@ -1618,8 +1618,8 @@ impl<T, B: HardwareIsolatedBacking>
}
}

impl<T, B: HardwareIsolatedBacking> hv1_hypercall::TranslateVirtualAddressX64
for UhHypercallHandler<'_, '_, T, B>
impl<B: HardwareIsolatedBacking> hv1_hypercall::TranslateVirtualAddressX64
for UhHypercallHandler<'_, '_, B>
{
fn translate_virtual_address(
&mut self,
Expand Down Expand Up @@ -2784,8 +2784,8 @@ impl<T: CpuIo, B: HardwareIsolatedBacking> TranslateGvaSupport for UhEmulationSt
}
}

impl<T, B: HardwareIsolatedBacking> hv1_hypercall::SendSyntheticClusterIpi
for UhHypercallHandler<'_, '_, T, B>
impl<B: HardwareIsolatedBacking> hv1_hypercall::SendSyntheticClusterIpi
for UhHypercallHandler<'_, '_, B>
{
fn send_synthetic_cluster_ipi(
&mut self,
Expand All @@ -2806,8 +2806,8 @@ impl<T, B: HardwareIsolatedBacking> hv1_hypercall::SendSyntheticClusterIpi
}
}

impl<T, B: HardwareIsolatedBacking> hv1_hypercall::SendSyntheticClusterIpiEx
for UhHypercallHandler<'_, '_, T, B>
impl<B: HardwareIsolatedBacking> hv1_hypercall::SendSyntheticClusterIpiEx
for UhHypercallHandler<'_, '_, B>
{
fn send_synthetic_cluster_ipi_ex(
&mut self,
Expand All @@ -2828,8 +2828,8 @@ impl<T, B: HardwareIsolatedBacking> hv1_hypercall::SendSyntheticClusterIpiEx
}
}

impl<T, B: HardwareIsolatedBacking> hv1_hypercall::InstallIntercept
for UhHypercallHandler<'_, '_, T, B>
impl<B: HardwareIsolatedBacking> hv1_hypercall::InstallIntercept
for UhHypercallHandler<'_, '_, B>
{
fn install_intercept(
&mut self,
Expand Down Expand Up @@ -2891,8 +2891,8 @@ impl<T, B: HardwareIsolatedBacking> hv1_hypercall::InstallIntercept
}
}

impl<T, B: HardwareIsolatedBacking> hv1_hypercall::AssertVirtualInterrupt
for UhHypercallHandler<'_, '_, T, B>
impl<B: HardwareIsolatedBacking> hv1_hypercall::AssertVirtualInterrupt
for UhHypercallHandler<'_, '_, B>
{
fn assert_virtual_interrupt(
&mut self,
Expand Down
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