Support -c codegen mode for Bluesim and Verilog#1
Open
nanavati wants to merge 1 commit into
Open
Conversation
nanavati
force-pushed
the
verilog-codegen-stage
branch
2 times, most recently
from
July 2, 2026 09:55
71daa54 to
42e379e
Compare
nanavati
added a commit
that referenced
this pull request
Jul 8, 2026
Sweeping a scratch build no longer requires touching target/release. The override travels via DIFFSWEEP_BSIM3 in the environment because Python 3.14 pool workers re-import the module (spawn/forkserver default) — a global assigned in main() silently reverts to the default binary in every worker, which is exactly how sweep #1 this session tested a stale binary. The chosen binary is printed at startup. Co-Authored-By: Claude Fable 5 <noreply@anthropic.com> Claude-Session: https://claude.ai/code/session_01DCK5eDnEJwUjaa46LFBUHP
nanavati
added a commit
that referenced
this pull request
Jul 10, 2026
Sweeping a scratch build no longer requires touching target/release. The override travels via DIFFSWEEP_TRS in the environment because Python 3.14 pool workers re-import the module (spawn/forkserver default) — a global assigned in main() silently reverts to the default binary in every worker, which is exactly how sweep #1 this session tested a stale binary. The chosen binary is printed at startup. Co-Authored-By: Claude Fable 5 <noreply@anthropic.com> Claude-Session: https://claude.ai/code/session_01DCK5eDnEJwUjaa46LFBUHP
nanavati
added a commit
that referenced
this pull request
Jul 10, 2026
Sweeping a scratch build no longer requires touching target/release. The override travels via DIFFSWEEP_TRS in the environment because Python 3.14 pool workers re-import the module (spawn/forkserver default) — a global assigned in main() silently reverts to the default binary in every worker, which is exactly how sweep #1 this session tested a stale binary. The chosen binary is printed at startup. Co-Authored-By: Claude Fable 5 <noreply@anthropic.com> Claude-Session: https://claude.ai/code/session_01DCK5eDnEJwUjaa46LFBUHP
Re-derivation of the verilog-codegen-stage work onto current upstream
main. Upstream has independently absorbed the foundational pieces this
stack originally introduced (the Bluesim codegen canonicalization and
the chunked/strict .ba serialization), so those are dropped here; what
remains is the novel feature:
* a -c codegen mode that generates a single module's code from its
elaborated .ba file, as a reusable block, for both back ends
(blockCodegen / codegenNames);
* writing .ba files by default for the Verilog back end, and removing
the dead Verilog-in-.ba machinery (genABinVerilog);
* treating an unusable or wrong-backend .ba as stale.
The .ba format tag is bumped (bsc-ba-20260712-2) because the Flags
record it embeds now differs from upstream's (blockCodegen and
codegenNames added, genABinVerilog removed). The Bin Flags serializer
is regenerated for the merged 135-field record, keeping upstream's
NOINLINE-chunked form and strict-ByteString reader.
Co-Authored-By: Claude Fable 5 <noreply@anthropic.com>
Claude-Session: https://claude.ai/code/session_01VVN2QMZtLUwkag1vCYLaao
nanavati
force-pushed
the
verilog-codegen-stage
branch
from
July 17, 2026 06:20
42e379e to
9330b63
Compare
nanavati
changed the title
This file contains hidden or bidirectional Unicode text that may be interpreted or compiled differently than what appears below. To review, open the file in an editor that reveals hidden Unicode characters.
Learn more about bidirectional Unicode characters
Sign up for free
to join this conversation on GitHub.
Already have an account?
Sign in to comment
1 participant
Add this suggestion to a batch that can be applied as a single commit.This suggestion is invalid because no changes were made to the code.Suggestions cannot be applied while the pull request is closed.Suggestions cannot be applied while viewing a subset of changes.Only one suggestion per line can be applied in a batch.Add this suggestion to a batch that can be applied as a single commit.Applying suggestions on deleted lines is not supported.You must change the existing code in this line in order to create a valid suggestion.Outdated suggestions cannot be applied.This suggestion has been applied or marked resolved.Suggestions cannot be applied from pending reviews.Suggestions cannot be applied on multi-line comments.Suggestions cannot be applied while the pull request is queued to merge.Suggestion cannot be applied right now. Please check back later.
Re-derivation of the verilog-codegen-stage work onto current upstream
main.Upstream has independently absorbed the foundational pieces this stack originally introduced (the Bluesim codegen canonicalization, and the chunked/strict
.baserialization), so those are dropped here; what remains is the novel feature:-ccodegen mode that generates a single module's code from its elaborated.bafile, as a reusable block, for both back ends (blockCodegen/codegenNames);.bafiles by default for the Verilog back end, and removing the dead Verilog-in-.bamachinery (genABinVerilog);.baas stale.The
.baformat tag is bumped (bsc-ba-20260712-2, and-3once-elab-onlyadds a field downstream) because theFlagsrecord it embeds now differs from upstream's (blockCodegen/codegenNamesadded,genABinVerilogremoved). TheBin Flagsserializer is regenerated for the merged record, keeping upstream'sNOINLINE-chunked form and strict-ByteStringreader.Validated on the re-derived base:
gen_mode(19),block_codegen(43),method_conditions(134),options(71), and the auto-mergedEResources/signal_namesgoldens all pass. Full-suite validation is left to CI (the merge touched ~300 testsuite golden files).Intended for upstream
B-Lang-org/bsc; opened on the fork because the integration cannot create upstream PRs.🤖 Generated with Claude Code
https://claude.ai/code/session_01VVN2QMZtLUwkag1vCYLaao