Add an -elab-only flag: stop compilation at the .ba#7
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With code generation available from a module's .ba alone (-c) and at link time, a compile no longer needs to produce backend output itself: with -elab-only, compilation stops after elaboration. For the Verilog backend that means genModuleVerilog is not run at all -- exactly as a Bluesim compile already behaves, verified by a test on the -v phase trace -- and each module's .v is generated later, from its .ba, by -c or by the link. The flag is backend-agnostic when compiling source: with -sim (or no backend) stopping at the .ba is already the behavior, so it is accepted as a no-op, letting build systems pass it unconditionally. Skipping codegen means the port properties that getIOProps deduces (const, reg, unused) are absent from the wrapper, as they always are for Bluesim, so a parent that re-exports such a port loses the deduced annotation in its .v header comment. Nothing structural consumes those deduced properties, so the generated modules are otherwise the same as a full compile's. The -u check correspondingly stops expecting .v files from an -elab-only compile, checking the .ba instead. The flag applies only when compiling source (S0100) -- including the no-filenames link path, which bypasses checkLinkFlags -- and cannot be combined with -no-elab, which would suppress the .ba that the deferred code generation needs (S0101). Co-Authored-By: Ravi Nanavati <ravi@matx.com> Co-Authored-By: Claude Fable 5 <noreply@anthropic.com> Claude-Session: https://claude.ai/code/session_01VVN2QMZtLUwkag1vCYLaao
Describe deferred code generation in the user guide's codegen-stage section and flag summary, and note in DEVELOP.md that -elab-only skips genModuleVerilog entirely, with the knock-on effect on deduced import-BVI port properties (annotation metadata only; nothing structural consumes them), and that the flag is a no-op for backends that already stop at the .ba. Co-Authored-By: Ravi Nanavati <ravi@matx.com> Co-Authored-By: Claude Fable 5 <noreply@anthropic.com> Claude-Session: https://claude.ai/code/session_01VVN2QMZtLUwkag1vCYLaao
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With code generation available from a module's .ba alone (
-c) and at link time (#2), a compile no longer needs to produce backend output itself: with-elab-only, compilation stops after elaboration. For the Verilog backend that meansgenModuleVerilogis not run at all — exactly as a Bluesim compile already behaves, verified by a test on the-vphase trace — and each module's .v is generated later, from its .ba, by-cor by the link. The flag is backend-agnostic when compiling source: with-sim(or no backend) stopping at the .ba is already the behavior, so it is accepted as a no-op, letting build systems pass it unconditionally.Skipping codegen means the port properties that
getIOPropsdeduces (const, reg, unused) are absent from the wrapper, as they always are for Bluesim, so a parent that re-exports such a port loses the deduced annotation in its .v header comment. Nothing structural consumes those deduced properties, so the generated modules are otherwise the same as a full compile's; the new testsuite directory checks byte-identity of-cand link output against a full compile for its design.The
-ucheck correspondingly stops expecting .v files from an-elab-onlycompile, checking the .ba instead (otherwise every recheck would recompile forever). The flag applies only when compiling source (S0100) — including the no-filenames link path, which bypassescheckLinkFlags— and cannot be combined with-no-elab, which would suppress the .ba that the deferred code generation needs (S0101).🤖 Generated with Claude Code
https://claude.ai/code/session_01VVN2QMZtLUwkag1vCYLaao
Generated by Claude Code