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IExpand: replace the SYB traversal in removeInlinedPositions#9

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claude/iexpand-syb-traversal-rw8p7e
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IExpand: replace the SYB traversal in removeInlinedPositions#9
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claude/iexpand-syb-traversal-rw8p7e

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Under -keep-method-conds, removeInlinedPositions strips the inlined-position bookkeeping from every ICon head once generateMethodPreds has harvested it into the COND defs. It did this with a Data.Generics "everywhere" traversal, which pays a generic-dispatch cost at every node of the module; on a large module the pass alone took about a third of elaboration time (and ~1 GB of rebuilt heap).

Replace it with a direct traversal over just the fields that carry expressions (local defs, rules, interface, state-instance args, clock/reset/inout wires, and the expression-bearing IConInfo constructors). The traversal is deliberately kept as lazy as the SYB one was: the output must stay byte-identical, and downstream declaration order depends on the order in which the generated names are first forced (FString interning feeds Ord Id, which feeds tsort tie-breaks and the Set-sorted lists in the Verilog backend). An earlier version that indexed the defs eagerly — a Map from def id to stripped body, to share ICValue rebuilds — reordered the generated Verilog; recursing into each ICValue payload directly avoids that and reproduces the SYB output exactly.

This is a performance change with no output difference. Correctness is covered by the existing bsc.misc/method_conditions tests, which check both the COND signals in the generated .v and the bluetcl position readout from the .ba (134 pass). Measured on a module elaborating to ~98k defs under -keep-method-conds, the pass dropped from ~27s to under a second.

🤖 Generated with Claude Code

https://claude.ai/code/session_01VVN2QMZtLUwkag1vCYLaao


Generated by Claude Code

Under -keep-method-conds, removeInlinedPositions strips the inlined-
position bookkeeping from every ICon head once generateMethodPreds has
harvested it.  It did so with a Data.Generics "everywhere" traversal,
which pays a generic-dispatch cost at every node of the module; on a
large module the pass alone took about a third of elaboration time.

Replace it with a direct traversal over just the fields that carry
expressions (defs, rules, interface, state-instance args, clock/reset/
inout wires, and the expression-bearing IConInfo constructors).  The
traversal is deliberately as lazy as SYB's was: the output must stay
byte-identical, and downstream declaration order depends on the order
in which the generated names are first forced (FString interning feeds
Ord Id, which feeds tsort tie-breaks and the Set-sorted lists in the
Verilog backend).  An earlier version that indexed the defs eagerly
(a Map from def id to stripped body, to share ICValue rebuilds)
reordered the generated Verilog; recursing into each ICValue payload
directly avoids that and reproduces the SYB output exactly.

Correctness is covered by the existing bsc.misc/method_conditions
tests (COND signals in the .v and bluetcl position readout from the
.ba); this is a performance change with no output difference.
Measured on a ~98k-def module compiled with -keep-method-conds, the
pass dropped from ~27s (and ~1 GB of rebuilt heap) to under a second.

Co-Authored-By: Ravi Nanavati <ravi@matx.com>
Co-Authored-By: Claude Fable 5 <noreply@anthropic.com>
Claude-Session: https://claude.ai/code/session_01VVN2QMZtLUwkag1vCYLaao
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