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    87 repositories

    • krg-infra

      Public
      Flake packages for Basic KRG Server Infrastructure
      Python
      •
      MIT License
      •1•0•72•4•Updated Jun 29, 2026Jun 29, 2026

    • aie4ml

      Public
      A plugin backend for hls4ml targeting AMD AI Engines (AIE)
      Python
      •
      Apache License 2.0
      •5•0•0•0•Updated Jun 27, 2026Jun 27, 2026

    • hls4ml

      Public
      Machine learning on FPGAs using HLS
      Python
      •
      Apache License 2.0
      •566•2•0•0•Updated Jun 24, 2026Jun 24, 2026

    • formal_axi

      Public
      Verilog
      •0•0•0•0•Updated Jun 21, 2026Jun 21, 2026

    • fuzz_symbfuzz

      Public
      Python
      •
      Apache License 2.0
      •2•0•0•0•Updated Jun 20, 2026Jun 20, 2026

    • fuzz_fuss

      Public
      FUSS: fuzzing on a shoestring
      C++
      •
      BSD 2-Clause "Simplified" License
      •1•0•0•0•Updated Jun 20, 2026Jun 20, 2026

    • arbolta

      Public
      Gate-level simulator for efficient hardware-software co-design.
      Rust
      •
      MIT License
      •3•0•0•0•Updated Jun 20, 2026Jun 20, 2026

    • FlooNoC

      Public
      A Fast, Low-Overhead On-chip Network
      SystemVerilog
      •
      Apache License 2.0
      •66•0•0•0•Updated Jun 19, 2026Jun 19, 2026

    • iDMA

      Public
      A modular, parametrizable, and highly flexible Data Movement Accelerator (DMA)
      SystemVerilog
      •
      Other
      •56•0•0•0•Updated Jun 19, 2026Jun 19, 2026

    • cgra4ml

      Public
      An Open Workflow to Build Custom SoCs and run Deep Models at the Edge
      asicaifpga
      asicaifpganeural-networkcnndnnverilogsystemverilogaxi-streamasic-design
      SystemVerilog
      •
      Apache License 2.0
      •27•124•3•2•Updated Jun 18, 2026Jun 18, 2026

    • esp

      Public
      Embedded Scalable Platforms: Heterogeneous SoC architecture and IP integration made easy
      C
      •
      Other
      •142•0•0•0•Updated Jun 17, 2026Jun 17, 2026

    • qualcomm-cluster

      Public
      0•0•0•0•Updated Jun 15, 2026Jun 15, 2026

    • caliptra-docker

      Public
      Caliptra + VCS
      Dockerfile
      •0•0•0•0•Updated Jun 9, 2026Jun 9, 2026

    • caliptra-rtl

      Public
      HW Design Collateral for Caliptra RoT IP
      SystemVerilog
      •
      Apache License 2.0
      •97•0•0•0•Updated Jun 9, 2026Jun 9, 2026

    • chipyard

      Public
      An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more
      Scala
      •
      BSD 3-Clause "New" or "Revised" License
      •879•0•0•0•Updated May 29, 2026May 29, 2026

    • taxi

      Public
      AXI, AXI stream, Ethernet, and PCIe components in System Verilog
      SystemVerilog
      •
      CERN Open Hardware Licence Version 2 - Strongly Reciprocal
      •124•0•0•0•Updated May 28, 2026May 28, 2026

    • particle_transformer_aie

      Public
      Python
      •2•2•0•0•Updated May 13, 2026May 13, 2026

    • waiter

      Public
      Waiter configurations
      Python
      •5•3•7•1•Updated May 11, 2026May 11, 2026

    • fabricant-prod

      Public
      fabricant.ucsd.edu configuration
      Python
      •1•0•5•0•Updated May 6, 2026May 6, 2026

    • ansible-components

      Public
      Collection of shared ansible scripts used by many servers in the KRG ecosystem
      0•0•0•0•Updated Apr 16, 2026Apr 16, 2026

    • fabricant-host

      Public archive
      Python
      •0•0•0•0•Updated Apr 16, 2026Apr 16, 2026

    • hls4ml-backend

      Public
      Python
      •0•1•0•0•Updated Mar 30, 2026Mar 30, 2026

    • gemmini

      Public
      Berkeley's Spatial Array Generator
      Scala
      •
      Other
      •274•0•0•0•Updated Mar 29, 2026Mar 29, 2026

    • cse160-docs

      Public
      Documentation for CSE 160
      C
      •8•2•2•4•Updated Mar 22, 2026Mar 22, 2026

    • cse160-opencl-docker

      Public
      Python
      •3•1•0•2•Updated Mar 10, 2026Mar 10, 2026

    • cse160-opencl

      Public
      C++
      •2•0•0•2•Updated Mar 10, 2026Mar 10, 2026

    • yosys-SVA-AXI4_FVIP

      Public
      YosysHQ SVA AXI Properties
      SystemVerilog
      •
      ISC License
      •9•0•0•0•Updated Mar 9, 2026Mar 9, 2026

    • fuzz_presifuzz

      Public
      Pre-Silicon Hardware Fuzzing Toolkit
      Rust
      •9•0•0•0•Updated Mar 5, 2026Mar 5, 2026

    • pulp_axi

      Public
      AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication
      SystemVerilog
      •
      Other
      •359•0•0•0•Updated Feb 21, 2026Feb 21, 2026

    • fuzz_hw_fuzzing_afl

      Public
      Fuzzer instrumentation for Verilog Fuzzing. Adds various coverage metrics, including Taint.
      C
      •
      Apache License 2.0
      •2•0•0•0•Updated Feb 15, 2026Feb 15, 2026
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