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1. eSC-V_project-link eSC-V_project-link Public

   Forked from ethycS0/eSC-V

   5 Stage Pipelined RV32I Zicsr SoC with Dual Port Synchronous Memory Controller and Bidirectional UART

   VHDL

2. DUAL-PORT-SRAM-90NM DUAL-PORT-SRAM-90NM Public

   Forked from ashwin6696/DUAL-PORT-SRAM-90NM

   RTL design of a dual-port SRAM in 90nm CMOS using Cadence. Includes synthesizable Verilog models, testbenches, and scripts for simulation, synthesis, and timing analysis, showcasing memory architec…

3. Headphone-Amplifier-project Headphone-Amplifier-project Public