[Zvdot4a8i] Extension for vector dot product (4-element, 8-bit integer) Version 0.1

[nibrunieAtSi5]

Specification of a new vector ISA extension for constant size (4D) vector dot product of integers (for now limited to 8-bit values).

This PR imports changes made by @kdockser and others in https://github.com/riscv/riscv-dot-product from the standalone repo to riscv-isa-manual. It also implements ARC's feedback.

• Tracking ticket: https://riscv.atlassian.net/browse/RVS-1971
• riscv-opcodes associated change: [Zvdot4a] Renaming Zvqdotq extension and vdotq instructions riscv-opcodes#402
• riscv-isa-sim (spike) associated change: [Zvdot4a] Renaming Zvqdotq to Zvdot4a and vdotq to vdot4a riscv-software-src/riscv-isa-sim#2212
• sail-riscv (formal model) associated change: [Zvdot4a8i] Adding description of Zvdot4a8i's vdot4a* instruction (BUILD but UNTESTED) sail-riscv#1495
• rvv-intrinsic-doc Intrinsics associated change: Zvqdotq zvdot4a8i renaming riscv-non-isa/riscv-rvv-intrinsic-doc#418

[aswaterman]

At least superficially this looks good. I think it's time to push it to the next stage in the process.

[topperc]

Should this mention that 4 elements are accmulated together? That would be more important if more SEWs become supported.

[topperc]

Should this say SEW/4-bit to match the vdota4u synopsis?

[nibrunieAtSi5]

Good idea, I think we could actually get rid of the SEW/4 mentions in the Title and Synopsys (the appear) later and focus on the fact that those are 4-element Dot Product Accumulates

[topperc]

Should this sentence be updated to say that vs1 is zero extended and vs2 is signed extended. Currently, the stence is identical to vdota4.

[nibrunieAtSi5]

I believe we always perform sign extension on the products (since this is signed-unsigned, the products are signed and must be sign extended).
The difference with respect to vdot4a is actually on the signedness of the product operands, so if we need to make a change it would be on the previous sentence (or mention that the products are signed values).

[topperc]

Ok. Re-reading that sentence it is just talking about widening the products before adding them together. It's not stated that the products are SEW/2 bits wide.

[4vtomat]

A question about naming, is there a specific reason tha we don't use zvdot32a8i as we have 32 bits accumulator? We have same scanerio in zvmm or xsfmm that number before a(accumulator) is accumulator size, e.g. xsfmm32a8i.

[aswaterman]

I would parse the name as "4-input dot product, with accumulation, of 8-bit integers". It's not that it's inconsistent with the matrix extensions; it's that the fixed-input dot-product instructions have a different naming scheme than the matrix extensions for legitimate reasons. I would argue that for a dot product with a fixed number of inputs, including that number in the name is more important.

(The accumulator being 32 bits is implied by the fact that this is a non-widening instruction, so the output elements are the same size as the input elements, i.e. 4x8.)

[topperc]

Is there a version number be we can use in toolchains? The 0.0.1 version in the existing spec for Zvqdotq has been giving us trouble in the toolchain riscv/riscv-dot-product#11

[nibrunieAtSi5]

Is there a version number be we can use in toolchains? The 0.0.1 version in the existing spec for Zvqdotq has been giving us trouble in the toolchain riscv/riscv-dot-product#11

I have added an implicit version number 6b0d5ef

This bumps it up from the original 0.0.1 (@aswaterman that the renaming mandated such a change anyway)