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robertcprice edited this page Mar 6, 2026 · 2 revisions

nCPU: A Neural CPU

A CPU where every arithmetic operation is a trained neural network.

Addition uses Kogge-Stone carry-lookahead. Multiplication uses a learned byte-pair lookup table. Bitwise ops use neural truth tables. Shifts use attention-based bit routing. No hardcoded arithmetic. All state lives on GPU as tensors. All computation stays on-device.


Key Results

Metric Value
Integer accuracy 100% on 32-bit signed domain
Trained models 24 actively wired (13 ALU + 11 neurOS)
Total models 30 production (.pt files)
Tests 850 passing across 15 test files
Assembly programs 62 verified programs (764 instructions)
Verification Exhaustive --- every possible sub-component input tested

Performance Highlights

Finding Detail
MUL is 12x faster than ADD Byte-pair LUT (21 us) vs Kogge-Stone CLA (248 us)
GPU side-channel immunity Zero cycle-count variance (sigma = 0.0 across 270 runs)
AES-128 T-table attacks Structurally impossible --- no data cache on GPU
neurOS self-compilation nsl source -> neural compiler -> neural assembler -> neural CPU -> correct results

Three Execution Tiers

Tier ALU Backend IPS What It Demonstrates
Neural Trained .pt models ~5K Exact neural arithmetic (the research contribution)
Fast Native tensor ops ~60K GPU-resident state with torch.add/torch.mul
Compute Metal compute shaders ~4M+ qemu-style GPU execution, zero CPU-GPU sync

Quick Start

pip install -e ".[dev]"

# Neural mode --- all arithmetic through trained neural networks
python main.py --program programs/fibonacci.asm

# GPU compute mode --- qemu-style Metal shader, ~4M IPS
python main.py --program programs/fibonacci.asm --compute

# GPU UNIX OS --- 25-command shell with fork/pipe/wait on Metal
python demos/gpu_os_demo.py --multiproc

Python API

# Neural mode
from ncpu.model import CPU
cpu = CPU(neural_execution=True)
cpu.load_program("MOV R0, 7\nMOV R1, 6\nMUL R2, R0, R1\nHALT")
cpu.run()
print(cpu.get_register("R2"))  # 42 --- computed by neural byte-pair LUT

# GPU compute mode
from kernels.mlx.ncpu_kernel import NCPUComputeKernel
kernel = NCPUComputeKernel()
kernel.load_program_from_asm("MOV R0, 7\nMOV R1, 6\nMUL R2, R0, R1\nHALT")
result = kernel.execute()  # ~4M IPS on Metal

What's Inside

Neural Arithmetic

Every ALU operation passes through a trained PyTorch model. Sub-components are exhaustively verified --- every possible input tested, providing a mathematical proof of correctness.

See: Neural Arithmetic | Models | ISA Reference

neurOS: Neural Operating System

Every OS component is a neural network --- 11 trained models, zero fallbacks. Self-compilation verified: nsl -> neural compiler -> neural assembler -> neural CPU.

See: neurOS

GPU-Native UNIX OS

A 25-command UNIX shell running as compiled C on Apple Silicon Metal GPU with multi-process support: fork, pipe, wait, dup2, signals.

See: GPU UNIX OS | GPU Demos

GPU Compute Mode

Metal compute shaders implementing nCPU ISA (21 opcodes, ~4.4M IPS) and ARM64 subset (130+ instructions, 42-61K IPS for compiled C).

See: GPU Compute Mode

Timing Side-Channel Immunity

GPU execution produces zero cycle-count variance. AES-128 T-table attacks are structurally impossible.

See: Side-Channel Immunity


Documentation

Page Description
Architecture Three execution tiers, pipeline, GPU-resident state
Neural Arithmetic CLA addition, byte-pair multiply, truth tables, shifts
Models All 24+ models with architectures, params, accuracy
neurOS 9-phase neural OS, 11 models, self-compilation
GPU Compute Mode Metal kernels, double-buffer architecture
GPU UNIX OS Multi-process, 25 commands, fork/pipe/wait
GPU Demos Crypto, games, VMs, HTTP server, MNIST
Side-Channel Immunity Zero-variance GPU timing, three-layer defense
Performance All benchmark results across all tiers
ISA Reference nCPU ISA encoding, ARM64 subset, syscalls
Development Project structure, testing, training, contributing

Research Paper

See the full research paper for detailed analysis, formal verification, and discussion of novel findings.

License

MIT

Author

Robert Price --- March 2026

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