Accelerating Local Laplacian Filters on FPGAs

This repository contains the complete implementation of a Local Laplacian Filter accelerator on FPGA using Bluespec SystemVerilog (BSV), along with supporting C code for data preparation and integration.

The design targets efficient execution of a three-level Local Laplacian Filter pipeline and focuses on high-performance convolution through a hardware-optimized architecture.

Repository Contents

• BSV source files implementing the hardware accelerator
• C source files for:
  • Input data preparation
  • Data combination and control
  • Host-side integration with the FPGA design

Reference Paper

Detailed explanation of the architecture and design methodology is provided in the accompanying paper:

Accelerating Local Laplacian Filters on FPGAs
https://arxiv.org/pdf/2402.12407

Key Design Features

• Shift-operation-based convolution engine
  Eliminates expensive multipliers to achieve faster and more resource-efficient convolution.

• Three-level Local Laplacian processing pipeline
  Optimized for parallelism and throughput on FPGA platforms.

• Hardware/software co-design
  BSV for hardware logic and C for data orchestration and preprocessing.

Purpose

This project demonstrates how algorithm–hardware co-design can significantly accelerate image processing workloads, specifically Local Laplacian Filters, on FPGA platforms.

Requirements

• Bluespec SystemVerilog (BSV) compiler
• FPGA vendor toolchain (e.g., Vivado)
• C compiler (GCC/Clang)
• Input image datasets (as described in the paper)

📌 Notes

• The current implementation supports three pyramid levels of the Local Laplacian Filter.
• The design prioritizes performance and resource efficiency over generality.