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  1. AMBA-Protocols AMBA-Protocols Public

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    5-stage riscv processor design using System Verilog

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  4. Asynchronous-FIFO-in-System-Verilog Asynchronous-FIFO-in-System-Verilog Public

    Designed an asynchronous FIFO of variable depth and width and overcome Clock domain crossing

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    2 core MESI Cache coherence protocol with shared memory

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    It's a UDP packet filter with(Ethernet Header + IP Header + UDP Header + UDP Payload)

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