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4 changes: 4 additions & 0 deletions cpp/VpiCallbacks.cpp
Original file line number Diff line number Diff line change
Expand Up @@ -233,6 +233,10 @@ auto vpi_start_of_sim_cb(p_cb_data cb_data_p) -> PLI_INT32 {

if (ngSpice_Init_Sync(ng_srcdata, nullptr, ng_sync, nullptr, nullptr) == 0) {
ngSpice_Command((char *)"bg_run");
if (ngSpice_running()==0) {
ERROR("Failed to initialize run ngspice.");
return 1;
}
} else {
ERROR("Failed to initialize ngSpice_Init_Sync interface.");
return 1;
Expand Down
7 changes: 7 additions & 0 deletions tests/error.cir
Original file line number Diff line number Diff line change
@@ -0,0 +1,7 @@
* test error

Vdd vdd 0 {ERROR_PARAM}

.tran 1ns 1

.end
16 changes: 16 additions & 0 deletions tests/error.v
Original file line number Diff line number Diff line change
@@ -0,0 +1,16 @@
`timescale 1ns/1ps

module error_cir();

endmodule

module error_tb();

error_cir error_cir ();

initial begin
$dumpfile("error.vcd");
$dumpvars (0);
end

endmodule
37 changes: 37 additions & 0 deletions tests/test_error.py
Original file line number Diff line number Diff line change
@@ -0,0 +1,37 @@
import cocotb
from cocotb.triggers import Timer
from cocotb.runner import get_runner
import os
from pathlib import Path
import spicebind
import pytest

@cocotb.test()
async def run_error_test(dut):
await Timer(10, units="ns")
# assert False, "Error"

@pytest.mark.xfail(reason="Expected error from spice simulation")
def test_error():
proj_path = Path(__file__).resolve().parent
sources = [proj_path / "error.v"]

sim = os.getenv("SIM", "icarus")

runner = get_runner(sim)
runner.build(
sources=sources,
hdl_toplevel="error_tb",
always=True,
)

runner.test(
hdl_toplevel="error_tb",
test_module="test_error,",
test_args=["-M", spicebind.get_lib_dir(), "-m", "spicebind_vpi"],
extra_env={"SPICE_NETLIST": str(proj_path / "error.cir"), "HDL_INSTANCE": "error_tb.error_cir"},
)


if __name__ == "__main__":
test_error()