A 2 stage CMOS OTA with Differential amplifier with active load as the first stage followed by Common Source stage using Cadence

A comprehensive VLSI design project implementing a static CMOS NAND gate using industry-standard Cadence tools and HSPICE simulation in 45nm technology.

32-bit Arithmetic-Logic Unit based on a hierarchical structure using VLSI

Designed and simulated ultra low-voltage, low-power CMOS 5:2 compressors in Cadence Virtuoso, based on Figure 13 from the referenced IEEE paper. Focused on optimizing power, delay, and area for efficient high-speed arithmetic circuits used in VLSI and DSP applications.

A practical day-by-day journey exploring Digital IC Design using Cadence Virtuoso — from schematics to layouts, DRC/LVS checks, parasitic extraction, and timing analysis.