vtr

Verilog to Routing -- Open Source CAD Flow for FPGA Research

This is a robotic package for an algorithm for visual teach and repeat

Virtual Telepresence Robot

Signal converter from Sony Beta 14-pin (K-type) camera to EIAJ 10-pin (J-type) VTR

FPGA acceleration vector matrix multiplication

Fast insert editing tool for broadcast-grade video — replace frames losslessly without re-encoding. Supports ProRes, DNxHD, XDCAM and more.

This Repo is a part of a 5-Day Workshop conducted by VLSI System Design (VSD) and the contents are divided Day wise for better understanding.

This is a Serial VTR emulator, running under Python. It simulates a VTR connected to a serial port of the computer.

A program for displaying the current time and text on a TV test chart and playing accompanying audio. Designed for amateur TV stations. Программа для вывода текущего времени и текста на тестовую ТВ таблицу и воспроизведения звукового сопровождения. Предназначена для любительских ТВ станций.

Hands-on FPGA fabric design using OpenFPGA and VTR, including architecture customization, RTL synthesis, placement, routing, Verilog fabric generation, and simulation.

Verified RTL optimization case studies: SHA-1, INT8 MatVec, and ML-KEM CBD, with correctness gates and paired VTR/PTM 45 nm evidence.

Huawei P10 specs, notes, infos for custom ROM dev