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contributions.tscircuit.com ・ tscircuit.com ・ Contribution Overviews ・ Changelogs

Generates weekly contribution overviews for tscircuit contributors. Check out all the contribution overviews here You can find AI-generated monthly changelogs in the changelogs directory

• All PRs in the tscircuit org are scanned/summarized via an LLM
• The LLM classifies each Diff/PR as into a set of attributes for scoring
• All the PRs, summaries, and classifications are organized into charts and tables for the website

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Current Week

Contribution Overview 2026-09-01

The current week is shown below. There are 3 major sections:

• Contributor Overview
• PRs by Repository
• PRs by Contributor
• Scoring & Sponsorship Details

PRs by Repository

pie
    "tscircuit/tscircuit" : 4
    "tscircuit/circuit-json" : 8
    "tscircuit/core" : 37
    "tscircuit/tscircuit.com" : 39
    "tscircuit/eval" : 51
    "tscircuit/runframe" : 61
    "tscircuit/cli" : 33
    "tscircuit/tscircuit-autorouter" : 37
    "tscircuit/schematic-trace-solver" : 20
    "tscircuit/circuit-json-to-kicad" : 12
    "tscircuit/biscuit-boards" : 7
    "tscircuit/check-shorts" : 4
    "tscircuit/fanout-solver" : 19
    "tscircuit/altiumts" : 13
    "tscircuit/copper-pour-solver" : 1
    "tscircuit/easyeda-converter" : 7
    "tscircuit/checks" : 5
    "tscircuit/circuit-json-to-altium" : 12
    "tscircuit/high-density-repair03" : 3
    "tscircuit/quick-configure" : 5
    "tscircuit/props" : 1
    "tscircuit/circuit-to-svg" : 2
    "tscircuit/svg.tscircuit.com" : 1
    "tscircuit/docs" : 4
    "tscircuit/high-density-repair02" : 1
    "tscircuit/ti" : 12
    "tscircuit/matchpack" : 3
    "tscircuit/circuit-json-to-gerber" : 4
    "tscircuit/high-density-repair01" : 1
    "tscircuit/implicit-copper-pour-solver" : 1
    "tscircuit/calculate-cell-boundaries" : 2
    "tscircuit/length-matching-solver" : 2
    "tscircuit/circuit-json-schematic-placement-analysis" : 1
    "tscircuit/high-density-a01" : 1
    "tscircuit/kicad-to-circuit-json" : 4
    "tscircuit/kicadts" : 1
    "tscircuit/dataset-srj32-trace-simplification" : 1
    "tscircuit/circuit-json-to-gltf" : 1
    "tscircuit/altium-to-circuit-json" : 1

Loading

Contributor Overview

Contributor	🐳 Major	🐙 Minor	🐌 Tiny	Score	⭐
seveibar	25	16	16	145	👑👑
mohan-bee	6	7	9	54	⭐⭐⭐
ShiboSoftwareDev	3	12	4	54	⭐⭐⭐
MustafaMulla29	5	3	9	36	⭐⭐
imrishabh18	6	3	2	33	⭐⭐
AnasSarkiz	3	0	1	20	⭐⭐
Abse2001	1	0	2	19	⭐⭐
rushabhcodes	1	2	7	16	⭐⭐
tscircuitbot	0	0	240	14	⭐⭐
techmannih	1	0	9	13.5	⭐⭐
hrithik18k	1	1	5	11	⭐⭐
GokulPandi-M	0	2	4	8	⭐
0hmX	1	0	2	7	⭐
KrishnaX12	0	0	6	6	⭐
Sang-it	0	1	3	5	⭐
anil08607	0	0	3	3

Staff Pass Ratio (SPR)

Contributor	Reviewed PRs	Rejections	Approvals	SPR
mohan-bee	4	0	4	100.0%
AnasSarkiz	3	0	3	100.0%
imrishabh18	2	0	2	100.0%
MustafaMulla29	2	0	2	100.0%
Abse2001	1	0	1	100.0%
GokulPandi-M	1	1	0	0.0%
hrithik18k	1	0	1	100.0%
KrishnaX12	1	1	0	0.0%
rushabhcodes	1	0	1	100.0%
ShiboSoftwareDev	1	0	1	100.0%

mohan-bee SPR PRs (4)

• #263 report two-terminal switches connected to themselves
• #37 preserve cell boundaries when preferred margins connect all cells
• #1061 collapse duplicate stubs on shared net branches
• #1017 keep downward ground labels directly below shared rails

AnasSarkiz SPR PRs (3)

• #3583 Fix duplicated traces in local autorouter stage output
• #2381 perf: cache repeated Pipeline 9 DRC candidates
• #99 consolidate native A11 and A12 solver foundations

imrishabh18 SPR PRs (2)

• #2328 Fix Bug Report 94 trace overlap in force solver
• #17 Preserve trace ordering during force improvement

MustafaMulla29 SPR PRs (2)

• #745 Add component ownership to PCB cutouts
• #1020 Align same-net pin exits, endpoint buses, and shared rails

Abse2001 SPR PRs (1)

• #229 Add complete Automotive Window Module example

GokulPandi-M SPR PRs (1)

• #241 fix: preserve clearance when aligning rail rows

hrithik18k SPR PRs (1)

• #748 feat: add styled schematic pin label runs

KrishnaX12 SPR PRs (1)

• #189 fix: keep USB OBJ models aligned with their footprints in 3D exports

rushabhcodes SPR PRs (1)

• #540 fix: derive CAD component size from model bounds

ShiboSoftwareDev SPR PRs (1)

• #3603 fix: preserve fanout handoff point identity

Note: AI evaluates PRs and assigns 1-3 star ratings automatically. 4 and 5 star ratings require manual staff review.

Review Table

Contributor	Reviews Received	Approvals Received	Rejections Received	Approvals	Rejections Given	PRs Opened	PRs Merged	Issues Created
0hmX	2	0	0	3	0	6	3	0
85heisenberg85	0	0	0	0	0	1	0	0
Abse2001	3	3	0	13	0	25	3	0
alondrn-hub	0	0	0	0	0	1	0	0
AnasSarkiz	4	4	0	8	0	14	4	0
anil08607	5	3	0	0	0	6	3	0
ardaerturk	0	0	0	0	0	1	0	0
beefrea	0	0	0	0	0	3	0	0
dyoung7293	0	0	0	0	0	1	0	0
fluxoutfluxin-tech	0	0	0	0	0	1	0	0
gcoinstash-cmd	0	0	0	0	0	21	0	0
GokulPandi-M	25	8	2	0	0	12	6	0
hrithik18k	17	11	1	0	0	16	7	0
imrishabh18	4	2	0	24	5	19	11	0
J2c-ashwani	0	0	0	0	0	1	0	0
KrishnaX12	14	8	1	0	0	18	6	0
mohan-bee	21	13	3	7	0	57	22	0
MustafaMulla29	11	10	0	6	0	19	17	0
mvennarini	0	0	0	0	0	8	0	0
NaveenAnantam	0	0	0	0	0	1	0	0
Navi1405	0	0	0	0	0	1	0	0
Rijul202	1	0	0	0	0	1	0	0
RohithPariki	0	0	0	0	0	1	0	0
rushabhcodes	22	11	0	1	0	10	10	0
sahil18z	0	0	0	0	0	2	0	0
Sang-it	0	0	0	0	0	5	4	0
seveibar	18	0	0	19	2	104	60	0
ShiboSoftwareDev	22	22	0	16	0	59	20	0
Sophia-Thickums	0	0	0	0	0	1	0	0
techmannih	5	3	0	1	0	20	10	0
tscircuitbot	0	0	0	0	0	306	240	0
waddle36	0	0	0	0	0	2	0	0
Wvdstoep	0	0	0	0	0	1	0	0

Changes by Repository

tscircuit/tscircuit

🐌 Tiny Contributions (4)

PR #	Impact	Contributor	Description
#4766	🐌 Tiny	tscircuitbot	Automated package update
#4763	🐌 Tiny	tscircuitbot	Automated package update
#4765	🐌 Tiny	rushabhcodes	Fixes copper pour solver to respect clearance around oval plated holes, preventing different-net pours from extending into required pad clearances.
#4762	🐌 Tiny	MustafaMulla29	Updates the versions of core and eval dependencies in the package.json file.

tscircuit/circuit-json

PR #	Impact	Rating	Contributor	Description
#745	🐳 Major	⭐⭐⭐	MustafaMulla29	Add an optional pcb_component_id to the shared PCB cutout schema to identify owning PCB components for footprint-defined cutouts, enabling better overlap checks.
#748	🐙 Minor	⭐⭐	hrithik18k	Adds structured text runs for schematic pin labels, allowing individual segments to be marked as overlined.
#754	🐙 Minor	⭐⭐	seveibar	Adds optional display_superscript: string to schematic text for inline net labels, allowing for display-only superscript suffixes while preserving original text and source_trace_id.
#750	🐙 Minor	⭐⭐	seveibar	Adds optional display_superscript: string to schematic net labels, allowing for display-only superscript suffixes without changing net identity.
#749	🐙 Minor	⭐⭐	seveibar	Adds source_confusing_net_name_warning for electrically disconnected source nets that share a name, such as separate GND nets in sibling subcircuits.

🐌 Tiny Contributions (3)

PR #	Impact	Contributor	Description
#755	🐌 Tiny	tscircuitbot	Automated package update
#753	🐌 Tiny	tscircuitbot	Automated package update
#751	🐌 Tiny	tscircuitbot	Automated package update

tscircuit/core

PR #	Impact	Rating	Contributor	Description
#3628	🐳 Major	⭐⭐⭐	MustafaMulla29	Propagates the owning pcb_component_id to rectangular, circular, and polygon footprint cutouts and adds a focused regression test for a cutout declared inside a chip footprint.
#3655	🐳 Major	⭐⭐⭐	seveibar	Exposes autorouter cache decisions and metadata during local autorouting lifecycle events, ensuring that routing experiments are accurate and not misled by stale routes.
#3581	🐳 Major	⭐⭐⭐	seveibar	Add a new autorouting phase that simplifies existing PCB traces and integrates with the autorouting pipeline, enhancing routing efficiency.
#3583	🐳 Major	⭐⭐⭐	AnasSarkiz	Fixes duplicated traces in the local autorouter stage output by ensuring that the current solver stage returns the correct trace data without reinserting it as new PCB copper.
#3594	🐙 Minor	⭐⭐	rushabhcodes	Refines schematic sheet warning assertions to ensure tests only check for relevant warnings, preventing false negatives due to unrelated warnings.
#3660	🐙 Minor	⭐⭐	seveibar	Populates display_superscript when a name is displayed on more than one source electrical network, ensuring disconnected GND nets in sibling subcircuits render as GND and GND, while connected copies share one suffix and unambiguous names have none.
#3650	🐙 Minor	⭐⭐	seveibar	Add fabrication notes for internally connected pads, including a path and label, while preserving component properties and excluding solder jumpers.
#3667	🐙 Minor	⭐⭐	GokulPandi-M	Fixes overlapping annotations in adjacent LED output branches, improving readability of component references and labels.
#3602	🐙 Minor	⭐⭐	ShiboSoftwareDev	Add an end-to-end DDR routing regression test for the AM62L32 and MT53E1G16D1ZW LPDDR4 packages, ensuring proper routing and DRC results.
#3603	🐙 Minor	⭐⭐	ShiboSoftwareDev	Fixes the synchronization of PCB breakout point identity on completed fanout traces before the global routing phase, allowing Pipeline 9 to recognize pre-routed copper as connected to the handoff endpoint and removing unnecessary detours in routing.

🐌 Tiny Contributions (27)

PR #	Impact	Contributor	Description
#3639	🐌 Tiny	tscircuitbot	Updates the tscircuitfanout-solver package from version 0.0.56 to 0.0.57
#3638	🐌 Tiny	tscircuitbot	Updates the tscircuitfanout-solver package from version 0.0.56 to 0.0.57
#3637	🐌 Tiny	tscircuitbot	Updates the tscircuitfanout-solver package from version 0.0.55 to 0.0.56
#3635	🐌 Tiny	tscircuitbot	Updates the tscircuitfanout-solver package from version 0.0.54 to 0.0.55
#3620	🐌 Tiny	tscircuitbot	Updates the tscircuitfanout-solver package from version 0.0.53 to 0.0.54
#3611	🐌 Tiny	tscircuitbot	Updates the tscircuitfanout-solver package from version 0.0.52 to 0.0.53 in the package.json file.
#3607	🐌 Tiny	tscircuitbot	Updates the tscircuitfanout-solver package from version 0.0.49 to 0.0.52
#3606	🐌 Tiny	tscircuitbot	Updates the tscircuitfanout-solver package from version 0.0.49 to 0.0.52
#3592	🐌 Tiny	tscircuitbot	Updates the tscircuitchecks package from version 0.0.179 to 0.0.180 in the package.json file.
#3591	🐌 Tiny	tscircuitbot	Updates the version of the tscircuitchecks package from 0.0.179 to 0.0.180 in package.json
#3579	🐌 Tiny	tscircuitbot	Updates the tscircuitfanout-solver package from version 0.0.48 to 0.0.49
#3588	🐌 Tiny	tscircuitbot	Updates the version of the tscircuitchecks package from 0.0.178 to 0.0.179 in package.json
#3578	🐌 Tiny	tscircuitbot	Updates the tscircuitfanout-solver package from version 0.0.47 to 0.0.48
#3623	🐌 Tiny	rushabhcodes	Refreshes the AM62L-to-LPDDR4 two-bus BGA fanout PCB snapshot to align the expected route geometry with the deterministic output from the fanout solver version 0.0.54, addressing a CI failure due to stale SVG geometry.
#3593	🐌 Tiny	rushabhcodes	Updates the tscircuitcopper-pour-solver dependency to version 0.0.52, enabling proper copper-pour handling for oval plated holes in PCB designs.
#3649	🐌 Tiny	MustafaMulla29	Updates the version of the schematic-trace-solver dependency from 0.0.178 to 0.0.183 in package.json
#3644	🐌 Tiny	MustafaMulla29	Bumps tscircuitchecks from 0.0.181 to 0.0.182, consuming the owned-footprint-cutout placement fix and outline-keepout compatibility fix from a related pull request.
#3625	🐌 Tiny	MustafaMulla29	Updates the version of the tscircuitchecks dependency from 0.0.180 to 0.0.181 in the package.json file.
#3582	🐌 Tiny	MustafaMulla29	Updates the tscircuitschematic-trace-solver dependency from version 0.0.175 to 0.0.178, including connector-crossing reroute improvements from a related pull request.
#3657	🐌 Tiny	seveibar	Bumps circuit-to-svg from 0.0.410 to 0.0.412 and refreshes affected schematic SVG snapshots to ensure sheet frames align with their contents.
#3653	🐌 Tiny	seveibar	Updates the tscircuitcapacity-autorouter dependency from version 0.0.866 to 0.0.874 while maintaining the existing peer dependency contract.
#3544	🐌 Tiny	seveibar	Summary increase the configured via drill from 0.10 mm to 0.15 mm while retaining the 0.24 mm via pad assert the configured board values and every emitted via dimension update the established progressive and two-bus visual snapshots in place without renaming them This is stacked on 3537, whose branch now includes merged PR 3541. Verification bun test testsreprosrepro-am62l-lpddr4-progressive-fanout.test.tsx --timeout 300000 bun test testsreprosrepro-am62l-lpddr4-two-bus-bga-fanout.test.tsx --timeout 300000 bunx biome check testsfixturescreate-am62l-lpddr4-fanout.tsx testsreprosrepro-am62l-lpddr4-progressive-fanout.test.tsx testsreprosrepro-am62l-lpddr4-two-bus-bga-fanout.test.tsx git diff --check All route geometry and via centers remain unchanged; the SVG visual difference is the larger drill circles. Manufacturing note A 0.15 mm hole inside a 0.24 mm pad leaves a 0.045 mm annular ring per side. The routing and current DRCs pass, but fabrication acceptance remains manufacturer-specific.
#3537	🐌 Tiny	seveibar	Summary add DDR_DMI0 as the eighth progressive DDR bus, routing AM62L DDR0_DM0 on F2 to LPDDR4 DMI0 on C3 route the singleton bus through inner5 with top-side exits on both component fanouts extend the exact phase, layer, exit, and connectivity assertions update the existing full-board visual snapshot in place without renaming it Dependency Depends on tscircuitfanout-solver112 and its next published release. package.json intentionally remains on tscircuitfanout-solver 0.0.45 until that release exists; this draft was validated against the local solver branch. Validation bun test testsreprosrepro-am62l-lpddr4-progressive-fanout.test.tsx 1 passed, 5,324 assertions bunx tsc --noEmit bunx biome check on changed TypeScript files visually inspected the updated full-board SVG snapshot
#3666	🐌 Tiny	imrishabh18	Updates the implicit copper pour solver dependency to a newer version that accounts for trace clearance and regenerates PCB snapshots for the nRF52810.
#3663	🐌 Tiny	mohan-bee	Updates the tscircuitchecks package from version 0.0.182 to 0.0.183 to enable the released same-net switch contact check in core, allowing board netlist checks to report shorted two-terminal switch contacts.
#3584	🐌 Tiny	techmannih	Reproduces the overlap between the adjacent AUDIO_VRA1, GND, and AUDIO_VRA2 fallback labels in the T113 schematic.
#3585	🐌 Tiny	techmannih	Add a minimal Trellis Core feedback network with L2, R5, C4, and R7 to reproduce the nearly overlapping BUCK_0V9_FB auto-label trace beside the R5-to-C4 trace and pin the behavior with a schematic snapshot.

tscircuit/tscircuit.com

PR #	Impact	Rating	Contributor	Description
#4729	🐳 Major	⭐⭐⭐	hrithik18k	Fixes schematic downloads to include all sheets in multi-sheet projects instead of just the firstdefault sheet.
#4748	🐳 Major	⭐⭐⭐	seveibar	Updates the editor URL when a workspace file is selected, preserving existing query parameters and clearing stale line selections, while adding a browser regression test for file selection URL sync.
#4735	🐳 Major	⭐⭐⭐	seveibar	Provides detailed error messages for avatar upload failures, including server rejection reasons and network issues, improving user guidance during upload attempts.
#4734	🐳 Major	⭐⭐⭐	seveibar	Fixes the issue where the editor opens lockfiles by default instead of the intended circuit entrypoint files, ensuring that only eligible files are selected for editing.

🐌 Tiny Contributions (35)

PR #	Impact	Contributor	Description
#4780	🐌 Tiny	tscircuitbot	Updates the tscircuitrunframe package from version 0.0.2658 to 0.0.2659
#4779	🐌 Tiny	tscircuitbot	Automated package update
#4778	🐌 Tiny	tscircuitbot	Automated package update
#4777	🐌 Tiny	tscircuitbot	Updates the tscircuiteval package from version 0.0.1345 to 0.0.1349 in the package.json file.
#4776	🐌 Tiny	tscircuitbot	Updates the tscircuitrunframe package version from 0.0.2656 to 0.0.2657 in package.json
#4774	🐌 Tiny	tscircuitbot	Automated package update
#4772	🐌 Tiny	tscircuitbot	Updates the tscircuitrunframe package from version 0.0.2653 to 0.0.2655
#4763	🐌 Tiny	tscircuitbot	Updates the tscircuitrunframe package from version 0.0.2646 to 0.0.2649
#4769	🐌 Tiny	tscircuitbot	Updates the tscircuiteval package version from 0.0.1343 to 0.0.1345 in package.json
#4764	🐌 Tiny	tscircuitbot	Updates the tscircuitrunframe package from version 0.0.2649 to 0.0.2650
#4768	🐌 Tiny	tscircuitbot	Updates the tscircuitrunframe package version from 0.0.2652 to 0.0.2653
#4767	🐌 Tiny	tscircuitbot	Automated package update for tscircuitrunframe from version 0.0.2651 to 0.0.2652
#4766	🐌 Tiny	tscircuitbot	Updates the tscircuitrunframe package from version 0.0.2650 to 0.0.2651
#4760	🐌 Tiny	tscircuitbot	Updates the tscircuiteval package from version 0.0.1342 to 0.0.1343
#4758	🐌 Tiny	tscircuitbot	Updates the tscircuiteval package to version 0.0.1342
#4755	🐌 Tiny	tscircuitbot	Updates the tscircuitrunframe package from version 0.0.2642 to 0.0.2645
#4757	🐌 Tiny	tscircuitbot	Updates the tscircuitrunframe package from version 0.0.2645 to 0.0.2646
#4743	🐌 Tiny	tscircuitbot	Updates the tscircuiteval package from version 0.0.1334 to 0.0.1335
#4742	🐌 Tiny	tscircuitbot	Updates the tscircuitrunframe package from version 0.0.2638 to 0.0.2639
#4752	🐌 Tiny	tscircuitbot	Updates the tscircuiteval package from version 0.0.1336 to 0.0.1338
#4746	🐌 Tiny	tscircuitbot	Automated package update
#4745	🐌 Tiny	tscircuitbot	Automated package update
#4744	🐌 Tiny	tscircuitbot	Updates the tscircuiteval package from version 0.0.1335 to 0.0.1336
#4741	🐌 Tiny	tscircuitbot	Updates the tscircuiteval package from version 0.0.1327 to 0.0.1334
#4740	🐌 Tiny	tscircuitbot	Updates the tscircuitrunframe package from version 0.0.2637 to 0.0.2638
#4738	🐌 Tiny	tscircuitbot	Updates the tscircuitrunframe package from version 0.0.2636 to 0.0.2637
#4736	🐌 Tiny	tscircuitbot	Updates the tscircuitrunframe package from version 0.0.2635 to 0.0.2636
#4733	🐌 Tiny	tscircuitbot	Automated package update
#4731	🐌 Tiny	tscircuitbot	Updates the tscircuitrunframe package from version 0.0.2633 to 0.0.2634
#4728	🐌 Tiny	tscircuitbot	Updates the tscircuitrunframe package from version 0.0.2632 to 0.0.2633
#4726	🐌 Tiny	tscircuitbot	Automated package update
#4724	🐌 Tiny	tscircuitbot	Automated package update
#4723	🐌 Tiny	tscircuitbot	Updates the tscircuiteval package from version 0.0.1323 to 0.0.1327
#4722	🐌 Tiny	tscircuitbot	Automated package update for tscircuitrunframe from version 0.0.2629 to 0.0.2630
#4720	🐌 Tiny	tscircuitbot	Automated package update

tscircuit/eval

🐌 Tiny Contributions (51)

PR #	Impact	Contributor	Description
#4373	🐌 Tiny	tscircuitbot	Automated package update
#4372	🐌 Tiny	tscircuitbot	Updates the version of several dependencies in the package.json file, including tscircuitcore and tscircuitimplicit-copper-pour-solver.
#4370	🐌 Tiny	tscircuitbot	Automated package update
#4369	🐌 Tiny	tscircuitbot	Updates package dependencies to their latest versions as part of routine maintenance.
#4367	🐌 Tiny	tscircuitbot	Automated package update
#4366	🐌 Tiny	tscircuitbot	Automated package update
#4363	🐌 Tiny	tscircuitbot	Automated package update
#4362	🐌 Tiny	tscircuitbot	Automated package update
#4361	🐌 Tiny	tscircuitbot	Automated package update
#4360	🐌 Tiny	tscircuitbot	Automated package update
#4353	🐌 Tiny	tscircuitbot	Automated package update
#4352	🐌 Tiny	tscircuitbot	Updates the versions of several dependencies in the package.json file.
#4347	🐌 Tiny	tscircuitbot	Updates the version of tscircuitcore from 0.0.1834 to 0.0.1835 and tscircuitfanout-solver from 0.0.56 to 0.0.57 in package.json
#4344	🐌 Tiny	tscircuitbot	Updates the version of tscircuitcore from 0.0.1833 to 0.0.1834 and tscircuitfanout-solver from 0.0.55 to 0.0.56 in package.json
#4341	🐌 Tiny	tscircuitbot	Updates the version of tscircuitcore from 0.0.1832 to 0.0.1833 and tscircuitfanout-solver from 0.0.54 to 0.0.55 in package.json
#4359	🐌 Tiny	tscircuitbot	Automated package update
#4358	🐌 Tiny	tscircuitbot	Updates the version of the tscircuitcore package from 0.0.1838 to 0.0.1839 in package.json
#4356	🐌 Tiny	tscircuitbot	Automated package update
#4355	🐌 Tiny	tscircuitbot	Automated package update
#4350	🐌 Tiny	tscircuitbot	Automated package update
#4349	🐌 Tiny	tscircuitbot	Automated package update
#4345	🐌 Tiny	tscircuitbot	Automated package update
#4342	🐌 Tiny	tscircuitbot	Automated package update
#4333	🐌 Tiny	tscircuitbot	Updates the version of tscircuitcore from 0.0.1829 to 0.0.1830 and tscircuitfanout-solver from 0.0.53 to 0.0.54 in package.json
#4330	🐌 Tiny	tscircuitbot	Updates the version of tscircuitcore from 0.0.1828 to 0.0.1829 and tscircuitfanout-solver from 0.0.52 to 0.0.53 in package.json
#4321	🐌 Tiny	tscircuitbot	Updates the version of the tscircuitcore package from 0.0.1825 to 0.0.1826 in package.json
#4340	🐌 Tiny	tscircuitbot	Automated package update
#4339	🐌 Tiny	tscircuitbot	Automated package update
#4337	🐌 Tiny	tscircuitbot	Automated package update
#4331	🐌 Tiny	tscircuitbot	Automated package update
#4328	🐌 Tiny	tscircuitbot	Automated package update
#4327	🐌 Tiny	tscircuitbot	Automated package update
#4325	🐌 Tiny	tscircuitbot	Automated package update
#4322	🐌 Tiny	tscircuitbot	Automated package update
#4336	🐌 Tiny	tscircuitbot	Automated package update
#4334	🐌 Tiny	tscircuitbot	Automated package update
#4324	🐌 Tiny	tscircuitbot	Updates the version of the tscircuitcore package from 0.0.1826 to 0.0.1827 in package.json
#4320	🐌 Tiny	tscircuitbot	Automated package update
#4319	🐌 Tiny	tscircuitbot	Automated package update
#4317	🐌 Tiny	tscircuitbot	Automated package update to version 0.0.1330
#4316	🐌 Tiny	tscircuitbot	Automated package update
#4314	🐌 Tiny	tscircuitbot	Automated package update to version 0.0.1329
#4313	🐌 Tiny	tscircuitbot	Automated package update
#4311	🐌 Tiny	tscircuitbot	Automated package update
#4310	🐌 Tiny	tscircuitbot	Automated package update
#4308	🐌 Tiny	tscircuitbot	Automated package update
#4307	🐌 Tiny	tscircuitbot	Updates package dependencies to their latest versions in package.json
#4305	🐌 Tiny	tscircuitbot	Automated package update
#4304	🐌 Tiny	tscircuitbot	Updates the version of several dependencies in the package.json file.
#4302	🐌 Tiny	tscircuitbot	Automated package update
#4301	🐌 Tiny	tscircuitbot	Updates package dependencies to their latest versions as part of routine maintenance.

tscircuit/runframe

🐌 Tiny Contributions (61)

PR #	Impact	Contributor	Description
#4982	🐌 Tiny	tscircuitbot	Automated package update
#4981	🐌 Tiny	tscircuitbot	Updates the tscircuiteval package to version 0.0.1350 in the package.json file.
#4980	🐌 Tiny	tscircuitbot	Automated package update
#4979	🐌 Tiny	tscircuitbot	Automated package update
#4978	🐌 Tiny	tscircuitbot	Automated package update
#4977	🐌 Tiny	tscircuitbot	Updates the tscircuiteval package to version 0.0.1348 in the package.json file.
#4976	🐌 Tiny	tscircuitbot	Automated package update
#4975	🐌 Tiny	tscircuitbot	Updates the tscircuiteval package to version 0.0.1347 in the package.json file.
#4974	🐌 Tiny	tscircuitbot	Automated package update
#4973	🐌 Tiny	tscircuitbot	Updates the tscircuiteval package to version 0.0.1346 in the package.json file.
#4955	🐌 Tiny	tscircuitbot	Automated package update
#4970	🐌 Tiny	tscircuitbot	Automated package update
#4969	🐌 Tiny	tscircuitbot	Updates the version of the circuit-json-to-gerber package from 0.0.102 to 0.0.103 in package.json
#4968	🐌 Tiny	tscircuitbot	Automated package update
#4965	🐌 Tiny	tscircuitbot	Automated package update
#4963	🐌 Tiny	tscircuitbot	Automated package update
#4954	🐌 Tiny	tscircuitbot	Automated package update
#4951	🐌 Tiny	tscircuitbot	Updates the tscircuiteval package from version 0.0.1337 to 0.0.1339 in the package.json file.
#4972	🐌 Tiny	tscircuitbot	Automated package update
#4971	🐌 Tiny	tscircuitbot	Updates the tscircuiteval package to version 0.0.1345 in the package.json file.
#4967	🐌 Tiny	tscircuitbot	Updates the circuit-json-to-kicad package to version 0.0.205 in package.json
#4964	🐌 Tiny	tscircuitbot	Updates the tscircuiteval package to version 0.0.1344 in the package.json file.
#4961	🐌 Tiny	tscircuitbot	Automated package update
#4960	🐌 Tiny	tscircuitbot	Updates the circuit-json-to-kicad package to version 0.0.204 in package.json
#4958	🐌 Tiny	tscircuitbot	Automated package update
#4957	🐌 Tiny	tscircuitbot	Updates the tscircuiteval package to version 0.0.1343 in the package.json file.
#4956	🐌 Tiny	tscircuitbot	Automated package update
#4953	🐌 Tiny	tscircuitbot	Updates the tscircuiteval package to version 0.0.1340 in the package.json file.
#4952	🐌 Tiny	tscircuitbot	Automated package update
#4962	🐌 Tiny	tscircuitbot	Updates the version of the circuit-json-to-gerber package from 0.0.101 to 0.0.102 in package.json
#4939	🐌 Tiny	tscircuitbot	Automated package update
#4930	🐌 Tiny	tscircuitbot	Updates the version of the circuit-json-to-kicad package from 0.0.200 to 0.0.201 in package.json
#4950	🐌 Tiny	tscircuitbot	Automated package update
#4949	🐌 Tiny	tscircuitbot	Updates the tscircuiteval package to version 0.0.1337 in the package.json file.
#4947	🐌 Tiny	tscircuitbot	Updates the circuit-json-to-kicad package version from 0.0.201 to 0.0.203 in package.json
#4942	🐌 Tiny	tscircuitbot	Updates the version of the circuit-json-to-gerber package from 0.0.100 to 0.0.101 in package.json
#4941	🐌 Tiny	tscircuitbot	Automated package update
#4940	🐌 Tiny	tscircuitbot	Updates the tscircuiteval package to version 0.0.1336 in the package.json file.
#4938	🐌 Tiny	tscircuitbot	Updates the tscircuiteval package to version 0.0.1335 in the package.json file.
#4937	🐌 Tiny	tscircuitbot	Automated package update
#4935	🐌 Tiny	tscircuitbot	Automated package update
#4932	🐌 Tiny	tscircuitbot	Updates the tscircuiteval package to version 0.0.1332 in the package.json file.
#4931	🐌 Tiny	tscircuitbot	Automated package update
#4943	🐌 Tiny	tscircuitbot	Automated package update
#4936	🐌 Tiny	tscircuitbot	Updates the tscircuiteval package to version 0.0.1334 in the package.json file.
#4934	🐌 Tiny	tscircuitbot	Updates the tscircuiteval package from version 0.0.1332 to 0.0.1333 in the package.json file.
#4933	🐌 Tiny	tscircuitbot	Automated package update
#4927	🐌 Tiny	tscircuitbot	Updates the tscircuiteval package to version 0.0.1331 in the package.json file.
#4926	🐌 Tiny	tscircuitbot	Automated package update
#4924	🐌 Tiny	tscircuitbot	Automated package update
#4923	🐌 Tiny	tscircuitbot	Updates the tscircuiteval package to version 0.0.1329 in the package.json file.
#4922	🐌 Tiny	tscircuitbot	Automated package update
#4921	🐌 Tiny	tscircuitbot	Updates the tscircuiteval package to version 0.0.1328 in the package.json file.
#4919	🐌 Tiny	tscircuitbot	Updates the tscircuiteval package to version 0.0.1327 in the package.json file.
#4918	🐌 Tiny	tscircuitbot	Automated package update
#4916	🐌 Tiny	tscircuitbot	Automated package update
#4915	🐌 Tiny	tscircuitbot	Updates the tscircuiteval package from version 0.0.1324 to 0.0.1325 in the package.json file.
#4928	🐌 Tiny	tscircuitbot	Automated package update
#4920	🐌 Tiny	tscircuitbot	Automated package update
#4925	🐌 Tiny	tscircuitbot	Updates the tscircuiteval package to version 0.0.1330 in the package.json file.
#4917	🐌 Tiny	tscircuitbot	Updates the tscircuiteval package to version 0.0.1326 in the package.json file.

tscircuit/cli

PR #	Impact	Rating	Contributor	Description
#4605	🐙 Minor	⭐⭐	seveibar	Shortens cache keys in autorouter logs for improved readability while retaining full cache keys in artifacts.
#4604	🐙 Minor	⭐⭐	seveibar	Adds detailed autorouter execution metadata including cache status and solver information to diagnostics and board metadata files.
#4590	🐙 Minor	⭐⭐	seveibar	Serializes concurrent tsci add invocations to prevent overlapping package-manager processes that can race on package.json, lockfiles, and native dependency installation.

🐌 Tiny Contributions (30)

PR #	Impact	Contributor	Description
#4609	🐌 Tiny	tscircuitbot	Updates the tscircuitrunframe package version from 0.0.2658 to 0.0.2659
#4608	🐌 Tiny	tscircuitbot	Updates the tscircuitrunframe package from version 0.0.2657 to 0.0.2658
#4607	🐌 Tiny	tscircuitbot	Updates the tscircuitrunframe package version from 0.0.2656 to 0.0.2657 in package.json
#4606	🐌 Tiny	tscircuitbot	Updates the tscircuitrunframe package from version 0.0.2655 to 0.0.2656
#4603	🐌 Tiny	tscircuitbot	Automated package update
#4602	🐌 Tiny	tscircuitbot	Updates the tscircuitrunframe package to version 0.0.2654
#4601	🐌 Tiny	tscircuitbot	Updates the tscircuitrunframe package version from 0.0.2652 to 0.0.2653 in package.json
#4600	🐌 Tiny	tscircuitbot	Updates the tscircuitrunframe package version from 0.0.2651 to 0.0.2652 in package.json
#4599	🐌 Tiny	tscircuitbot	Updates the tscircuitrunframe package from version 0.0.2650 to 0.0.2651
#4598	🐌 Tiny	tscircuitbot	Updates the tscircuitrunframe package to version 0.0.2650 in package.json
#4597	🐌 Tiny	tscircuitbot	Updates the tscircuitrunframe package from version 0.0.2648 to 0.0.2649
#4596	🐌 Tiny	tscircuitbot	Updates the tscircuitrunframe package from version 0.0.2647 to 0.0.2648
#4595	🐌 Tiny	tscircuitbot	Updates the tscircuitrunframe package to version 0.0.2647 in package.json
#4594	🐌 Tiny	tscircuitbot	Updates the tscircuitrunframe package from version 0.0.2645 to 0.0.2646
#4593	🐌 Tiny	tscircuitbot	Updates the tscircuitrunframe package from version 0.0.2644 to 0.0.2645
#4589	🐌 Tiny	tscircuitbot	Updates the tscircuitrunframe package version from 0.0.2642 to 0.0.2644 in package.json
#4587	🐌 Tiny	tscircuitbot	Updates the tscircuitrunframe package from version 0.0.2641 to 0.0.2642
#4586	🐌 Tiny	tscircuitbot	Updates the tscircuitrunframe package to version 0.0.2641 in package.json
#4585	🐌 Tiny	tscircuitbot	Updates the tscircuitrunframe package version from 0.0.2639 to 0.0.2640
#4584	🐌 Tiny	tscircuitbot	Updates the tscircuitrunframe package from version 0.0.2638 to 0.0.2639
#4583	🐌 Tiny	tscircuitbot	Updates the tscircuitrunframe package to version 0.0.2638
#4582	🐌 Tiny	tscircuitbot	Updates the tscircuitrunframe package to version 0.0.2637 in package.json
#4581	🐌 Tiny	tscircuitbot	Updates the tscircuitrunframe package from version 0.0.2635 to 0.0.2636
#4579	🐌 Tiny	tscircuitbot	Updates the tscircuitrunframe package from version 0.0.2633 to 0.0.2634
#4576	🐌 Tiny	tscircuitbot	Updates the tscircuitrunframe package from version 0.0.2630 to 0.0.2631
#4580	🐌 Tiny	tscircuitbot	Updates the tscircuitrunframe package to version 0.0.2635 in the package.json file.
#4578	🐌 Tiny	tscircuitbot	Updates the tscircuitrunframe package to version 0.0.2633
#4577	🐌 Tiny	tscircuitbot	Updates the tscircuitrunframe package from version 0.0.2631 to 0.0.2632
#4575	🐌 Tiny	tscircuitbot	Updates the tscircuitrunframe package to version 0.0.2630 in package.json
#4574	🐌 Tiny	tscircuitbot	Updates the tscircuitrunframe package to version 0.0.2629 in package.json

tscircuit/tscircuit-autorouter

PR #	Impact	Rating	Contributor	Description
#2402	🐳 Major	⭐⭐⭐	seveibar	Fixes via span DRC evaluation to include all layers in the reference DRC, ensuring accurate collision detection and preserving staged repairs during autorouting.
#2407	🐳 Major	⭐⭐⭐	seveibar	Add --dataset srj33 to the benchmark and run-sample loaders, and a Cosmos benchmark fixture for all 31 original bug-report inputs from dataset-srj33-drc-failures.
#2399	🐳 Major	⭐⭐⭐	seveibar	Fixes autorouting issues by preserving connected-pad boundaries during Pipeline9 repair, preventing backwards kinks in traces entering their own pads.
#2393	🐳 Major	⭐⭐⭐	seveibar	Adds a collision-checked vertex cleanup pass to Pipeline11s path simplifier, reducing redundant vertices and improving route quality on the RP2040 motor controller.
#2390	🐳 Major	⭐⭐⭐	seveibar	Fixes autorouting failure by excluding obstacles connected to a route in the Pipeline9 repair process, ensuring that the repair solver does not displace traces away from their own pads.
#2349	🐳 Major	⭐⭐⭐	seveibar	Reuses static connectivity during DRC repair in Pipeline9 to improve performance and reduce timeouts.
#2370	🐳 Major	⭐⭐⭐	seveibar	Fixes the autorouting progress reporting for Pipeline 7 and Pipeline 9, ensuring accurate progress updates during routing operations.
#2335	🐳 Major	⭐⭐⭐	seveibar	Summary add numbered AutoroutingPipelineSolver11_Simplification, a cleanup-only pipeline for existing SimpleRouteJson.traces use the conventional BasePipelineSolver definition with explicit prepare, simplify, apply, and DRC-validation stages; the outer pipeline does not override _step() keep stage work incremental: one input trace, one wrapped solver step, one output trace, or one validation pass per _step() preserve variable-width traces exactly and include them as immutable collision geometry while simplifying constant-width traces opt Pipeline 11 into clearance checks that use the actual currentneighbor trace widths and a matching spatial-search margin, without changing established pipeline behavior preserve trace IDs, connection metadata, endpoints, terminal vias, and terminal PCB-port metadata without routing missing SRJ connections Why The simplify autorouting phase needs a dedicated local pipeline for users who want to improve traces that are already routed. Reusing the normal autorouting pipeline would solve SRJ connections again instead of limiting the work to post-route cleanup. The cleanup solvers currently use one traceThickness per high-density route. Sending a variable-width SRJ trace through that representation collapsed every segment to one arbitrary width and created DRC violations. Pipeline 11 now makes that capability boundary explicit: constant-width routes are simplified, while variable-width routes retain their exact copper geometry and still block unsafe shortcuts. Companion props PR: https:github.qkg1.toptscircuitpropspull723 Real-board visual snapshot The fixture was captured from the board and MCU autorouting events produced by imrishabh18rp2040-motor-controller(https:tscircuit.comimrishabh18rp2040-motor-controllerfiles) at tscircuitrp2040-motor-controllerb4560e5(https:github.qkg1.toptscircuitrp2040-motor-controllercommitb4560e5). Pipeline 11 preserves all 148 traces and every input width set, including 30 exact variable-width routes. It reduces route points from 1,829 to 1,763 and vias from 150 to 73, while exact relaxed DRC remains 0 0. !RP2040 motor controller before and after Pipeline 11 simplification(https:raw.githubusercontent.comtscircuittscircuit-autorouterfeatsimplification-pipelinetests__snapshots__pipeline11-simplification-rp2040-motor-controller-visual-rp2040-motor-controller-before-after.snap.svg) Validation bun run build bunx tsc --noEmit focused Pipeline 11 suite: 4 tests passed Pipeline 9 reference-clean exact-output regression test passed real-board test: all width sets preserved, 30 variable-width routes exact, exact relaxed DRC 0 0 visual snapshot regenerated, rendered to PNG, and inspected git diff --check GitHub CI: all 9 test shards, build, type-check, format-check, added-code check, and Vercel checks passed
#2328	🐳 Major	⭐⭐⭐	imrishabh18	Fixes trace overlap issue in the force solver related to Bug Report 94, ensuring no overlaps remain in the autorouting process.
#2381	🐳 Major	⭐⭐⭐	AnasSarkiz	Caches exact repeated indexed DRC results during Pipeline 9 joint repair, limits the candidate cache to 64 entries, and exposes cache diagnostics for performance tracking.
#2361	🐳 Major	⭐⭐⭐	ShiboSoftwareDev	Fixes autorouters relaxed DRC to accept trace endpoints only when they geometrically touch same-net copper on the same PCB layer, preventing false disconnected endpoint errors.

🐌 Tiny Contributions (26)

PR #	Impact	Contributor	Description
#2411	🐌 Tiny	tscircuitbot	Automated package update
#2409	🐌 Tiny	tscircuitbot	Automated package update
#2408	🐌 Tiny	tscircuitbot	Automated package update
#2400	🐌 Tiny	tscircuitbot	Automated package update
#2398	🐌 Tiny	tscircuitbot	Automated package update
#2397	🐌 Tiny	tscircuitbot	Automated package update
#2394	🐌 Tiny	tscircuitbot	Automated package update
#2388	🐌 Tiny	tscircuitbot	Automated package update
#2386	🐌 Tiny	tscircuitbot	Automated package update
#2384	🐌 Tiny	tscircuitbot	Automated package update
#2355	🐌 Tiny	tscircuitbot	Automated package update
#2354	🐌 Tiny	tscircuitbot	Automated package update
#2377	🐌 Tiny	tscircuitbot	Automated package update
#2373	🐌 Tiny	tscircuitbot	Automated package update
#2371	🐌 Tiny	tscircuitbot	Automated package update
#2343	🐌 Tiny	tscircuitbot	Automated package update
#2338	🐌 Tiny	tscircuitbot	Automated package update
#2336	🐌 Tiny	tscircuitbot	Automated package update
#2334	🐌 Tiny	tscircuitbot	Automated package update
#2404	🐌 Tiny	seveibar	Relaxed DRC count overlay The snapshots now show a computed Relaxed DRC errors overlay using the reusable libtestinggetBugReportSnapshotSvg.ts helper. This baseline records Pipeline7: 32 and Pipeline9: 31, using standard benchmark relaxed rules (no board-specific overrides). The helper evaluates existing and new copper together, honors replacement metadata, and renders the same copper. The bug-report creation script now uses it, and the visualization skill documents its usage for future bug reports. Unit tests cover the actual count, input preservation, replaced copper, and explicit rule overrides. The bugreport104 snapshot tests remain test.skip. Merge this baseline before 2389 Capture the complete routed pedometer board on current main (450af9cb90d50880a96f62e9babafc79678031a1) before adopting the fine-pitch pad-escape repair in 2389. This PR changes no solver code or dependencies. Add the pre-route bugreport104 capture and remove its remaining preloaded traces (traces: ). The older public capture is a post-route board with routed-via obstacles, so clearing only its traces is not a valid pre-route input. Point the interactive bugreport104 fixture at that trace-free pre-route capture. Commit separate Pipeline7 and Pipeline9 solved-board SVG snapshots, generated with mains own dependencies and caching disabled. Keep both snapshot tests as test.skip, as requested. They were temporarily enabled locally to generate the snapshots and verify both solvers complete. Render the actual emitted routes, pads, and vias on white; omit connection-debug dots so they do not obscure the BGA escapes. These snapshots record current-main output, not a zero-DRC claim. The exact same input, test files, and SVG paths are used by 2389, which commits the repaired outputs. Merge this PR first so 2389 shows ordinary beforeafter SVG modifications instead of new snapshot files. Manual snapshot regeneration Temporarily change test.skip to test in the two bugreport104-pedometer-pipeline-solved.test.ts files, then run: sh BUN_UPDATE_SNAPSHOTS1 bun test testsbugsbugreport104-pedometer-pipeline7-solved.test.ts testsbugsbugreport104-pedometer-pipeline9-solved.test.ts --timeout 9999999 Restore test.skip before committing or pushing. Both snapshot tests were run locally; TypeScript and the production build were also checked. Main baseline previews Pipeline7 !Pipeline7 current-main solved pedometer board(https:raw.githubusercontent.comtscircuittscircuit-autorouter5f6e4a3dc179461052315a6351b0e414ddc55fe0testsbugs__snapshots__bugreport104-pedometer-pipeline7-solved.snap.svg) Pipeline9 !Pipeline9 current-main solved pedometer board(https:raw.githubusercontent.comtscircuittscircuit-autorouter5f6e4a3dc179461052315a6351b0e414ddc55fe0testsbugs__snapshots__bugreport104-pedometer-pipeline9-solved.snap.svg)
#2392	🐌 Tiny	seveibar	Adds a fixture for the RP2040 motor controller that creates Pipeline11s simplification solver in the autorouting debugger, validated with existing tests and preserves all traces while reducing vias.
#2387	🐌 Tiny	seveibar	Summary add a debugger fixture for seveibarpedometer v1.0.6(https:tscircuit.comseveibarpedometer?version1.0.6pcb) preserve the exact partially routed input: 4 layers, 42 mm 26 mm bounds, 304 obstacles, 142 preloaded traces, and 11 remaining connections capture the routing regression around the U2_CHARGER BGA, where preloaded traces run beneath the BGA footprint Current behavior Pipeline7: reaches highDensityRouteSolver but does not complete; the local reproduction was stopped after more than two minutes in that stage Pipeline9: reports solved: true even though Pipeline9HighDensitySolver.stats.nodeCount is 0; its output contains the same 142 preloaded traces and none of the 11 requested connection names Expected behavior Pipeline7 and Pipeline9 should both route the 11 remaining connections while preserving and correctly reasoning about the preloaded traces beneatharound the BGA. Validation bunx tsc --noEmit bun run build reproduced Pipeline7 with bun scriptsrun-sample.ts --pipeline 7 --srj-path downloaded-pedometer-routes.json reproduced Pipeline9 with bun scriptsrun-sample.ts --pipeline 9 --srj-path downloaded-pedometer-routes.json verified the committed SRJ is structurally identical to the downloaded v1.0.6 simpleRouteJson payload This is a fixture-only bug report; it intentionally does not include an autorouter fix.
#2333	🐌 Tiny	seveibar	Limits the benchmark-all command to only run on dataset01 and dataset18, updates benchmark instructions, and modifies the workflow assertion in the benchmark command test.
#2342	🐌 Tiny	mohan-bee	Updates the length-matching solver dependency to the latest commit for improved functionality and bug fixes.
#2385	🐌 Tiny	AnasSarkiz	Summary add the pedometer Simple Route JSON as bugreport103-pedometer load the large reproduction from publicfixtures in the autorouting debugger Validation verified the JSON parses and has the expected autorouter shape confirmed the committed reproduction matches the supplied board byte-for-byte tests not run, per request (fixture-only change)
#2326	🐌 Tiny	0hmX	Adds a reproduction of the QFP16 Pipeline 9 with extra vias, documenting a routing-quality regression without changing solver behavior.

tscircuit/schematic-trace-solver

PR #	Impact	Rating	Contributor	Description
#1054	🐳 Major	⭐⭐⭐	MustafaMulla29	Fixes unnecessary doglegs in schematic traces by refining corner pin direction handling and improving routing algorithms to minimize turns and collisions with labels.
#1020	🐳 Major	⭐⭐⭐	MustafaMulla29	Aligns adjacent same-side pin exits onto neighboring pin rows, aligns degree-two buses between perpendicular endpointload traces, and preserves generated connector junctions while validating candidates against various criteria.
#1013	🐳 Major	⭐⭐⭐	MustafaMulla29	Reroutes component-to-component traces to avoid crossings with generated net-label connectors, ensuring cleaner routing and preserving valid label-to-label crossings.
#1064	🐳 Major	⭐⭐⭐	mohan-bee	Fixes trace recovery to prioritize local routes over perimeter detours, improving routing efficiency and accuracy.
#1061	🐳 Major	⭐⭐⭐	mohan-bee	motivation same-net ground junction alignment can retain two traces over the same endpoint stub. before img width128 height122 altimage srchttps:github.qkg1.topuser-attachmentsassets145d8d34-aad0-4538-93a1-66cb486acccc the existing esp-12f repro contains duplicate shared-endpoint geometry. after img width112 height72 altimage srchttps:github.qkg1.topuser-attachmentsassetsb4720501-e8fd-44d9-8a26-2c4c7599f94c the solver uses typed ground metadata to preserve one physical pin connection and end the redundant trace at the existing junction. the focused geometry test and affected regression snapshots are updated; no extra before snapshot is added.
#1017	🐳 Major	⭐⭐⭐	mohan-bee	Adjusts the placement of downward ground labels to ensure they remain close to their connected pins and directly attached to shared rails, improving schematic clarity and accuracy.
#1038	🐳 Major	⭐⭐⭐	techmannih	Fixes the issue where net label connectors run parallel to host traces by shifting them laterally onto their existing host trace and creating a direct tee instead of a near-parallel connector.
#1052	🐙 Minor	⭐⭐	MustafaMulla29	Prevents anchored label connectors from creating strict perpendicular crossings with unrelated traces, ensuring safer label placements in schematic designs.
#1045	🐙 Minor	⭐⭐	mohan-bee	Merges adjacent same-net branches that share their first segment onto nearby parallel rails, improving schematic alignment.
#1008	🐙 Minor	⭐⭐	mohan-bee	Prevents duplicate ground labels on unwired pins of a component to ensure correct schematic representation.

🐌 Tiny Contributions (10)

PR #	Impact	Contributor	Description
#1063	🐌 Tiny	tscircuitbot	Adds a snapshot-only regression test and debugger page for the attached JSON solver input.
#1037	🐌 Tiny	tscircuitbot	Adds a snapshot-only regression test and debugger page for the attached JSON solver input.
#1035	🐌 Tiny	tscircuitbot	Adds a snapshot-only regression test and debugger page for the attached JSON solver input.
#1050	🐌 Tiny	MustafaMulla29	Add a focused schematic trace reproduction for the two mouse switches, capturing solver input and snapshotting the unnecessary horizontal jog in the vertical GND trunk.
#1047	🐌 Tiny	MustafaMulla29	Reproduces an unnecessary dogleg in the RF1 trace between two nominally aligned inductors, providing a focused test case without implementing solver changes.
#1044	🐌 Tiny	MustafaMulla29	Add an isolated reproduction of the capacitor-side VBAT label crossing the long CHG_STAT trace, using the exact InputProblem emitted by tscircuitcore 0.0.1829 at commit b761dc8, while retaining specific components and adding a focused solver SVG snapshot.
#1048	🐌 Tiny	mohan-bee	Adds a flag to mark ground nets in various bug report and repro input JSON files to indicate they are ground connections.
#1043	🐌 Tiny	mohan-bee	Adds a seven-component input fixture and SVG snapshot test for the isolated power section of board 8090, preserving its routing topology as a regression case.
#1016	🐌 Tiny	mohan-bee	This pull request introduces a new JSON file containing the schematic trace for a USB hub sheet. The file includes detailed information about various chips, their dimensions, and pin configurations, which are essential for the schematic representation of the USB hub.
#1002	🐌 Tiny	mohan-bee	Adds a focused solver snapshot for the smartwatch power sheet routing case, which was previously unaddressed.

tscircuit/circuit-json-to-kicad

PR #	Impact	Rating	Contributor	Description
#502	🐙 Minor	⭐⭐	GokulPandi-M	Fixes the omission of 3D models in KiCad exports for components that only have OBJ URLs by deriving and embedding corresponding STEP models from EasyEDA.
#490	🐙 Minor	⭐⭐	ShiboSoftwareDev	Bumps kicad-to-circuit-json to 0.0.122 and implements side-by-side comparisons of native KiCad renders with Circuit JSON round-trip outputs, validating SVG renderability without modifying checked-in source files.
#494	🐙 Minor	⭐⭐	ShiboSoftwareDev	Exports component fabrication-note paths as fp_line graphics on F.Fab or B.Fab, preserving component-relative placement, rotation, and stroke width.

🐌 Tiny Contributions (9)

PR #	Impact	Contributor	Description
#510	🐌 Tiny	tscircuitbot	Automated package update
#505	🐌 Tiny	tscircuitbot	Automated package update
#493	🐌 Tiny	tscircuitbot	Automated package update
#501	🐌 Tiny	tscircuitbot	Automated package update
#500	🐌 Tiny	tscircuitbot	Automated package update
#497	🐌 Tiny	GokulPandi-M	Adds a characterization reproduction for a bottom-mounted display model in KiCad, isolating the model transform issue without fixing it.
#496	🐌 Tiny	GokulPandi-M	Reproduces the omission of the OBJ-only USB-C model in KiCad export, confirming that the connector body is missing while the footprint remains.
#491	🐌 Tiny	ShiboSoftwareDev	Preserves imported KiCad component-level symbol artwork instead of overlaying generic chip symbols, maintains native fills, text placement, colors, and standalone schematic graphics, and refreshes all native source-versus-converted schematic snapshots with explicit snapshot-test timeouts.
#495	🐌 Tiny	ShiboSoftwareDev	Fixes the EBAZ4205 schematic rendering issue caused by KiCad 10s upgrade process, ensuring original multi-unit selections are preserved and the correct layout is maintained.

tscircuit/biscuit-boards

PR #	Impact	Rating	Contributor	Description
#103	🐙 Minor	⭐⭐	Sang-it	Adds a uniform solderpaste layer by reducing pad dimensions and applying lens distortion for non-circular top pads in LightBurn exports.

🐌 Tiny Contributions (6)

PR #	Impact	Contributor	Description
#111	🐌 Tiny	tscircuitbot	Automated package update
#109	🐌 Tiny	tscircuitbot	Automated package update
#104	🐌 Tiny	tscircuitbot	Automated package update
#108	🐌 Tiny	Sang-it	Add STM32 and RP2040 photodiode examples for BiscuitBoard V2, including routing through prefabricated vias and adding PCB snapshots and tests.
#106	🐌 Tiny	Sang-it	Add the independent 75 x 55 mm BiscuitBoard V2 clad with 2.5 mm-pitch corner and center via fields, and copy the STM32TMC5130 controller onto V2 with placements defined directly in the controller TSX and prefabricated-via routing.
#110	🐌 Tiny	Sang-it	Restores the includeBoardFiles configuration removed by a previous PR, retaining all 20 previously included example board entries.

tscircuit/check-shorts

PR #	Impact	Rating	Contributor	Description
#53	🐙 Minor	⭐⭐	seveibar	Fixes truncation of bitmap legend labels by implementing glyph-width-aware fitting based on available legend row width, ensuring full labels are displayed when they fit and adding an ellipsis only at the right edge.

🐌 Tiny Contributions (3)

PR #	Impact	Contributor	Description
#54	🐌 Tiny	tscircuitbot	Automated package update
#52	🐌 Tiny	tscircuitbot	Automated package update
#51	🐌 Tiny	mohan-bee	Updates the circuit-json-to-gerber dependency to version 0.0.101 in the package.json file.

tscircuit/fanout-solver

PR #	Impact	Rating	Contributor	Description
#149	🐳 Major	⭐⭐⭐	seveibar	Summary add bounded local dogbone repair and displaced-via routing for constrained differential pairs add adaptive top-edge plane candidate selection with causal reservation refinement add a dataset31 reductiondebug script plus reduced and full SVG regression snapshots improve the dataset31 benchmark from 112 to 212 without regressing the existing left-center pass Benchmark Command: .benchmark.sh --concurrency 4 --sample-timeout-seconds 120 solved 212 02-top-center: 135135, validated, 86.61s 11-left-center: 135135, validated, 15.43s remaining 10 samples: 120s timeout Verification bun test: 152 pass, 0 fail bun run typecheck bun run format:check git diff --check originmain focused reduced snapshot test after generated SVG whitespace cleanup
#141	🐳 Major	⭐⭐⭐	seveibar	AM62L progressive routing can stall after the fanout-solver update: the initial dense route strands a signal, then repeatedly searches winding paths in a synchronous fallback that prevents Buns test timeout from firing. Core CI hits its 15-minute job limit. Retry coordinated routing before the broad fallback, cache A edge-clearance checks per terminal, and retain ordinary dogbone candidates when automatically matched sites fail. This restores the complete progressive route and one via per connection in the two-bus DRAM case. Route both top-facing layouts with their original timing constraints: Repro 04: route all 135 connections and plane drops before length tuning. Its test no longer removes differential pairs or skew limits. Dataset-fanout31 sample 02-top-center: add the exact capture and a debugger sample with explicit plane reservation hints. Route all 135 connections with 135 through-vias, keeping all original geometry, differential pairs, bus skew limits, and 102 plane terminations. The centered case also requires consistent clearance handling when a winding path leaves its own source pad, corner-aware boundary vias, and joint selection of plane routes when a greedy choice blocks another drop. Enumerate singleton plane candidates once instead of repeatedly regenerating their prefixes. For length matching, revisit excessive detours against completed copper and allow a differential pairs outer lane to move aside before tuning its mate. Searches retain bounded attempts, and complete copper is revalidated before accepting a result. Validation: Top-center regression: 135 connections, 135 through-vias, full routed-copper DRC and original timing constraints pass; 34.7 seconds locally on Bun 1.4.0 and 101.0 seconds in CI. Includes SVG snapshot and capture generator. Constrained Repro 04 passes with its existing snapshot in 7.5 seconds locally and 24.4 seconds in CI, previously 36.2 seconds locally. RAM-left full solve retains its snapshot. Progressive capture passes full DRC with its existing snapshot. Configured corner routing is isolated so the ordinary progressive fanout remains identical to the previously passing output. Typecheck and formatting pass. Single-pass enumeration reproduces all 136 previously captured plane candidates exactly and in order. Earlier Bun CPU profiles of the initial timeout fix reduced the isolated solve from 11.6 to 5.3 seconds with collision caching alone; the published 0.0.51 case was still searching at 30 seconds. Those measurements precede the additional top-facing fixes. Final solver commit 9da1d4c passes all eight test shards, typecheck, formatting, and Vercel. Core commit 40ba64e also passes all ten test shards, typecheck, formatting, smoke test, and Vercel with the final pin. Core dependency update: https:github.qkg1.toptscircuitcorepull3605
#138	🐳 Major	⭐⭐⭐	seveibar	Summary Route all 135135 AM62L fanout connections in the RAM-left 11-left-center sample from dataset-fanout31-am62l(https:github.qkg1.toptscircuitdataset-fanout31-am62lblob8c73befb36b125c84651c07454a9b940b3c6500asamples11-left-center.tsx), with no validation issues. The complete case takes about 46 seconds locally on the first layer assignment. The captured input is unchanged: all 573 pad obstacles, 102 plane drops, nine DDR signal buses, three differential pairs, and original clearance and length-skew constraints are retained. The upstream sample contains no decoupling capacitors. Scope: AM62L fanout only; this does not complete the RAM fanout or inter-chip DDR routing. Routing changes Align the fine winding grid to the pad lattice to find narrow inter-via channels, and add bounded blocked-terminal route-order retries. Coordinate dogbone sites and avoid reserving corner-bus vias inside a neighboring wide buss source field. Let an embedded singleton such as RESET escape on its source layer, then use one via near the boundary to reach its assigned layer. Match plane sites against the actual routed copper, retaining provisional sites when possible during length matching. Preserve the existing explicitly configured dense-routing path and small-bus ordering. Reproduction and visual coverage Add Dataset 08 with the exact upstream input, a pinned TSXcore capture script, and a timeout-bounded diagnostic CLI. Add input, BYTE1, planes-plus-address, and full-solve SVG regression tests using solver.visualize(). Refresh two existing SoC routing snapshots for the new valid route geometry; the prior top-edge repro keeps its existing snapshot. Full solved SVG(https:github.qkg1.toptscircuitfanout-solverblobtestdataset-fanout31-ram-lefttests__snapshots__fanout31-am62l-left-solved.snap.svg) sh bun scriptssolve-fanout31-left.ts --timeout-ms 120000 --max-layer-combinations 1 --output tmpfanout31-left Validation bun test: 136 passed, 0 failed, across 95 files (348 seconds). bun run typecheck: passed. bun run format:check: passed; oversized-fixture warnings only. bun run build:site: passed. The existing parallel CI test discovery includes the new tests automatically.
#134	🐳 Major	⭐⭐⭐	seveibar	Summary make component dogbone matching account for full-board obstacles and already-routed vias reserve selected dense plane drops before boundary buses and solve the remaining constrained plane routes with a bounded compatibility search add a binary-reduction debug harness plus the committed TSX generator input add a solved 135-connection solver.visualize() SVG regression snapshot Verification bunx tsc --noEmit bunx biome check ... 9 focused routing tests pass, including all 135 connections in the snapshot regression full captured DDR skew run: 111111 buses, 135135 connections, 0 failed buses
#129	🐳 Major	⭐⭐⭐	seveibar	Summary add a Cosmos debugger repro for the AM62L nine-bus top-edge breakout failure commit the RAM-above circuit source in scriptsgenerate-reprogenerate-repro04.tsx render that TSX with tscircuitcore using RootCircuit.renderUntilSettled() override the SOC_FANOUT algorithmFn to capture the real fanout-solver input and return a completed no-op autorouter regenerate the committed inputSrj, options fixture without manually rotating or redistributing points retain 135 connections, 589 phase obstacles, eight layers, nine DDR signal buses, 102 plane-drop buses, and three differential pairs verify that all 33 downstream breakout points are on the top boundary snapshot getSvgFromGraphicsObject(solver.visualize()) so the complete RAM-above input geometry and top-edge targets are visually reviewed The generator dependency workspace keeps the current core rendering stack separate from fanout-solvers pinned runtime capacity-autorouter version. Run it with bun run generate:repro04. Current behavior The captured circuit is the AM62L failure case: the solver is unable to complete the 135-connection breakout. The Cosmos page exposes the full solver search for inspection. Verification bun run generate:repro04 (deterministic SHA-256 across repeated runs) bun run typecheck bun test testsam62l-top-edge-breakout-repro.test.ts bun test with the repository-local Bun 1.3.2 (128 pass, 0 fail before the visual assertion was added) bun run build:site git diff --check CI note Format, type-check, Vercel, and the new AM62L repro test pass. The Bun 1.4 CI test job reports an existing SVG snapshot mismatch in am62l-lpddr4-progressive-through-all-dram-repro.test.ts; the same mismatch occurred on this PR before the generator and AM62L visualization commits, while that snapshot passes locally under Bun 1.3.2.
#131	🐳 Major	⭐⭐⭐	seveibar	Summary move candidate-layer probing out of the constructor and expose assignment and grouped-beam work as active subsolvers break dense through-all routing into visible dense-routing and boundary-bus subsolvers advance via-minimal winding A in bounded 5,000-state batches, with route-order, connection, batch, and expanded-state progress in solver stats give every active work solver a phase-aware visualize() view; boundary routing renders the current grid, frontier, expanded states, active via, and best path render adaptive single-layer progress while obstacle nodes are classified, the flow network is built and augmented, and routes are extracted preserve the synchronous routing APIs by consuming the same incremental generators to completion without constructing debug graphics batch single-layer adaptive grid, terminal, graph, and max-flow work across steps Bus-atomic routing, scoring, and accepted final geometry remain unchanged. Repro03 Before the split, one repro03 step() spent about 17.4 seconds routing all three dense boundary buses. It is now 432 observable iterations, including 307 boundary-search steps. A measured full solve completed in 19.7 seconds with a 182 ms maximum step and a 177 ms maximum boundary-search step while live visualization state was enabled. The active debugger chain during the hotspot is: FanoutAssignmentSolver DenseMixedTerminationSolver BoundaryBusRoutingSolver Successive calls to visualize() during that boundary subsolver now show the A frontier and newly expanded states changing between batches. Testing bun run typecheck bun test on Bun 1.3.2: 129 passed, 0 failed focused repro03 incremental-step and live-visualization regression adaptive single-layer live-visualization regression existing repro03 126-connection routing and DRC regression bun run format:check git diff --check CI note The hosted Bun 1.4 test job reaches 124 passing tests, including both repro03 tests, but the pre-existing nine-bus DRAM SVG snapshot mismatch also reproduces on current main; the workflow then exceeds its five-minute timeout. Baseline run: https:github.qkg1.toptscircuitfanout-solveractionsruns33295395301
#150	🐙 Minor	⭐⭐	seveibar	Fixes routing failure in browser Web Workers due to the absence of Nodes process global, ensuring debug flags are accessible without crashing.
#144	🐙 Minor	⭐⭐	seveibar	Summary Make .benchmark.sh, bun run benchmark, and the Blacksmith benchmark workflow run only the 12 directional AM62L cases from tscircuitdataset-fanout31-am62l. Reject other dataset selections. Capture the exact inputs from the pinned upstream TSXcore sample factories before timing, save them under benchmark-resultsinputs, and benchmark this checkouts solver. Retain all 135 connections, 573 pad obstacles, 111 buses, and the original routing constraints. Show only dataset 31 totals and per-sample results in reports and PR comments. Record the dataset revision, reject legacymixed-dataset reports, and include captured inputs in the CI artifact. Remove the legacy SRJ19SRJ29 benchmark scripts and obsolete benchmark workflows. Keep all regression datasetstests and solver code unchanged. Use a frozen lockfile in the benchmark workflow and update the documentation. Verification 8 focused benchmark tests pass (245 assertions), covering all 12 upstream captures, input preservation, CLIreport output, dataset selection, validation, process isolation, and PR authorization. The freshly captured 11-left-center input and solver options exactly match the existing fixture. A normal-deadline RAM-left benchmark solves and validates 135135 connections (56.01 seconds locally). An all-12-case smoke run with an intentionally short 2-second deadline confirms complete execution and reporting; those timeout results are not a performance baseline. Typecheck, formatting, workflow lint, frozen-lockfile installation, and diff checks pass. Formatting retains three existing oversized-fixture warnings. The trusted benchmark comment renderer changes after this PR is merged into the default branch.

🐌 Tiny Contributions (11)

PR #	Impact	Contributor	Description
#155	🐌 Tiny	tscircuitbot	Automated package update
#153	🐌 Tiny	tscircuitbot	Automated package update
#152	🐌 Tiny	tscircuitbot	Automated package update
#146	🐌 Tiny	tscircuitbot	Automated package update
#145	🐌 Tiny	tscircuitbot	Automated package update
#137	🐌 Tiny	tscircuitbot	Automated package update
#142	🐌 Tiny	tscircuitbot	Automated package update
#133	🐌 Tiny	tscircuitbot	Automated package update
#132	🐌 Tiny	tscircuitbot	Automated package update
#140	🐌 Tiny	seveibar	Add a new benchmarking workflow that runs all available samples, records results, and provides a status update via PR comments.
#154	🐌 Tiny	0hmX	Summary add the exact northeast SoC and DRAM breakout SRJs under testsfixturessoc-dramnortheast add a selectable Cosmos debugger page using GenericSolverDebugger and FanoutSolver add a focused characterization test and SVG snapshots for both fixtures Current solver behavior This PR intentionally does not change solver logic. Both fixtures exhaust 256 layer assignments and fail with FanoutSolver: best layer assignment routed 033 connections. The current inferred directions are up for the SoC and down for the DRAM. Verification bun test testssoc-dram-northeast-failure.test.ts bun run typecheck

tscircuit/altiumts

PR #	Impact	Rating	Contributor	Description
#115	🐙 Minor	⭐⭐	ShiboSoftwareDev	Adds support for binary polygon cutout regions by serializing them with a native region kind and ensuring proper validation and parsing of their properties.

🐌 Tiny Contributions (12)

PR #	Impact	Contributor	Description
#129	🐌 Tiny	tscircuitbot	Automated package update
#114	🐌 Tiny	tscircuitbot	Automated package update
#127	🐌 Tiny	tscircuitbot	Automated package update
#112	🐌 Tiny	tscircuitbot	Automated package update
#121	🐌 Tiny	hrithik18k	Fixes rendering of Altium schematic arcs to correctly handle angles crossing zero degrees, ensuring accurate representation of wrapped arcs.
#117	🐌 Tiny	hrithik18k	Reproduces the rendering difference of a magnetic-core inductor in the schematic compared to Altium Designer without changing renderer behavior.
#113	🐌 Tiny	hrithik18k	Fixes the issue where the renderer uses incorrect dimensions for predefined Altium sheets, ensuring complete schematics are displayed according to selected sheet sizes.
#111	🐌 Tiny	hrithik18k	Reproduces a valid PowerSupply schematic appearing blank due to content being clipped outside the page boundary.
#131	🐌 Tiny	KrishnaX12	Fixes the SVG renderer to correctly display active component display modes for polarized capacitors in schematics.
#119	🐌 Tiny	KrishnaX12	Fixes schematic bus rendering using the actual Altium record model by parsing and rendering Bus and BusEntry records accurately.
#99	🐌 Tiny	KrishnaX12	Fixes rendering order of opaque component graphics to ensure pin labels are not obscured by filled component bodies.
#98	🐌 Tiny	KrishnaX12	Fixes rendering of active-low overbars in schematic SVG text by parsing Altium negation markers and rendering them correctly in SVG format.

tscircuit/copper-pour-solver

PR #	Impact	Rating	Contributor	Description
#86	🐳 Major	⭐⭐⭐	rushabhcodes	Fixes the omission of oval plated holes in copper pour calculations, ensuring proper clearance and thermal relief for designs using oval plated holes.

tscircuit/easyeda-converter

PR #	Impact	Rating	Contributor	Description
#540	🐙 Minor	⭐⭐	rushabhcodes	Fixes incorrect CAD component size calculation by deriving dimensions from the models bounding box instead of PCB footprint dimensions, ensuring accurate rendering of components.

🐌 Tiny Contributions (6)

PR #	Impact	Contributor	Description
#543	🐌 Tiny	rushabhcodes	Fixes rendering of the C7519 schematic by preserving the fill color and visibility of protection diodes, correcting a bug where the fill color was incorrectly displayed as the outline color.
#542	🐌 Tiny	rushabhcodes	Reproduces a bug where the C7519 schematic renders incorrectly as a solid red rectangle instead of the expected design, providing a baseline for future fixes.
#539	🐌 Tiny	rushabhcodes	Adds a regression test for the C165948 CAD footprint size mismatch issue, recording the incorrect emitted CAD size metadata and providing a 3D snapshot for visibility.
#534	🐌 Tiny	rushabhcodes	Reproduces a bug where HTML-encoded pin aliases from EasyEDA are incorrectly processed, leading to invalid pin labels in generated components.
#538	🐌 Tiny	GokulPandi-M	Fixes the issue where the import of the C2941005 component loses four schematic terminals, ensuring all six terminals are represented in the schematic and PCB.
#535	🐌 Tiny	Abse2001	Documents real L0805 inductor reproductions with provenance and source-identity checks for two EasyEDALCSC component records, ensuring accurate representation in generated schematics and PCBs.

tscircuit/checks

PR #	Impact	Rating	Contributor	Description
#259	🐙 Minor	⭐⭐	MustafaMulla29	Fixes placement errors for components over their own footprint cutouts by ignoring such errors during validation and adds a regression test to ensure correct behavior.
#257	🐙 Minor	⭐⭐	MustafaMulla29	Fixes clearance geometry calculations for plated-hole pill and oval copper pads to ensure accurate DRC checks without false errors.
#262	🐙 Minor	⭐⭐	mohan-bee	Add a test and schematic snapshot for a pushbutton whose two schematic contacts connect to the same net, addressing a previously captured failure in Circuit JSON.
#263	🐙 Minor	⭐⭐	mohan-bee	Detects two-terminal pushbuttons and switches whose schematic contacts connect to the same net, emitting a fatal configuration error for misconfigured components.

🐌 Tiny Contributions (1)

PR #	Impact	Contributor	Description
#256	🐌 Tiny	MustafaMulla29	Reproduces the two 0 mm pad-clearance errors from the unmodified generated component EC10E1220505 in a regression test, including a PCB SVG snapshot with error visualization enabled.

tscircuit/circuit-json-to-altium

PR #	Impact	Rating	Contributor	Description
#105	🐳 Major	⭐⭐⭐	ShiboSoftwareDev	Preserves component ownership for native copper regions, matching solder-mask openings, and retains polygon-cutout provenance for Altium PCB antenna designs.
#52	🐙 Minor	⭐⭐	ShiboSoftwareDev	Preserves mechanical and drill-layer PCB text during conversion to Altium format, ensuring that previously lost text elements are retained in the output.
#101	🐙 Minor	⭐⭐	ShiboSoftwareDev	Resolves Altium component parameter expressions to their actual values in the generated Circuit JSON, ensuring that converted schematics display the correct component text instead of formulas.
#103	🐙 Minor	⭐⭐	ShiboSoftwareDev	Adds support for importing and preserving Altium silkscreen graphics, including filled overlay regions with interior holes, and enhances structural coverage for PiDP silkscreen graphics.
#102	🐙 Minor	⭐⭐	ShiboSoftwareDev	Preserves native child-sheet filenames during the source comparison process and ensures they are reused when generating Altium schematic documents, while also deduplicating shared hierarchical documents by case-insensitive filename.
#104	🐙 Minor	⭐⭐	ShiboSoftwareDev	Preserves Altium board cutouts and slot rotation during conversion from Circuit JSON to Altium, ensuring accurate representation of mechanical features.

🐌 Tiny Contributions (6)

PR #	Impact	Contributor	Description
#106	🐌 Tiny	hrithik18k	Pins altiumts to a specific commit to validate the predefined Altium sheet-sizing fix in the converter before merging another PR, ensuring all converter tests pass with the corrected dimensions.
#92	🐌 Tiny	techmannih	Fixes the handling of filled rectangle colors in Altium exports by using the rectangles color as a fallback when fill_color is omitted and preserving fill_color when provided, affecting both component symbols and sheet annotations.
#93	🐌 Tiny	techmannih	Fixes the handling of fractional coordinates in Altium schematics by ensuring they use a five-digit fixed-point representation, preventing rendering issues in native Altium viewers.
#100	🐌 Tiny	KrishnaX12	Pins the altiumts component to the merged v0.0.41 main commit and refreshes schematic SVG snapshots affected by the corrected component body and pin-label paint order.
#115	🐌 Tiny	anil08607	Adds support for newer Altium RECORD209 note objects that were previously dropped during schematic round trips, converting these notes into schematic text and filled rectangle annotations, preserving the original note content and appearance instead of silently losing them.
#119	🐌 Tiny	anil08607	Updates the altiumts dependency to a newer commit version in package.json

tscircuit/high-density-repair03

PR #	Impact	Rating	Contributor	Description
#99	🐳 Major	⭐⭐⭐	seveibar	Changes the via span API to exclusively use from_layer and to_layer, removing the optional layers field and ensuring DRC and Circuit JSON conversion derive the inclusive board-layer span from required endpoints.
#96	🐳 Major	⭐⭐⭐	seveibar	Normalizes DRC checks for vias to include all layers in their span, ensuring accurate collision detection across multiple layers without altering input geometry.
#92	🐳 Major	⭐⭐⭐	seveibar	Fixes DRC to ensure that vias are validated across their physical layer spans, preventing routing errors that could short copper on intermediate layers.

tscircuit/quick-configure

PR #	Impact	Rating	Contributor	Description
#12	🐳 Major	⭐⭐⭐	seveibar	Top now rebuilds from TSX with all 33 DDR signals connected through the CPU and RAM fanouts. There are zero vias between the fanouts, and every Top via pad is contained in a fanout region. The checked-in Top preview is freshly generated and shows all three routing-phase boundaries. The layout uses the working Right reference topology rotated 90: the CPU is at (0, -9.5), rotated 90, and RAM is at (-1.81916, 9.616917), rotated 180. This changes the earlier dataset layouts CPU orientation. Each position retains a separate TSX configuration. Top includes both packages powerground fanout and eight DDR capacitors; Right additionally includes the references 60 direct processor decouplers. Both Top fanouts explicitly run fanout solver 0.0.54 through cores fanout preset. The adapter preserves cores paired exit coordinates, layers, completed-footprint keepouts, and prior copper. Winding and fanout planning run in the horizontal reference frame and return their results in board coordinates. This handles windings orientation-dependent ordering; CPU coordinates are normalized to 12 decimals while RAM retains native rotation precision because the current solvers tied track ordering is numerically sensitive. The global phase joins matching exits directly and rejects layer mismatches or copper errors. Core 0.0.1830 is pinned with the small unreleased presethandoff patch from tscircuitcore3610. The patch, lockfile, TSX, and build scripts are available in the unzipped source browser. No saved SVG or circuit JSON is used as a routing input. Both positions also expose captured routing-phase data, including the routed traces. Validation: Rebuilt both configurations from TSX with npm run build:ddr, then assembled the actual public previews. Top: CPU 135135 connections, RAM 143143, all 33 global DDR signals connected, 327 PCB traces checked, zero copper errors, and zero vias outside fanouts. Ran the exact core regression testsreprosrepro-am62l-lpddr4-progressive-fanout.test.tsx with solver 0.0.54: 1 pass, 11,483 assertions, including its existing snapshot without updating it. The initial Right rebuild using its original dependency set also reproduced the previously checked-in SVG byte for byte. All 53 repository tests, TypeScript, and git diff --check pass. Regression checks cover coordinated exits, winding order under rotation, exported phase copper, physical DDR connectivity, and rejection of an outside-fanout via. Clean Ubuntu CI run(https:github.qkg1.toptscircuitquick-configureactionsruns33769713673) passed installation, both TSX builds, site assembly, all tests, and TypeScript. The new workflow rebuilds both boards before testing, so stale preview files cannot hide a solver failure. Vercel preview deployment also passed. Visually inspected the generated PCB SVG. In-app browser navigation was blocked by an automatic approval-review service error (404).
#11	🐳 Major	⭐⭐⭐	seveibar	Adds a DDR Breakouts page at ddr-breakouts, reachable from the header alongside Sensors Displays. The three dropdowns offer AM62L, MT53E1G16D1ZW (LPDDR4), and RAM Position. Right is implemented; Top, Left, and Bottom are visible but disabled. The Right board ports cores progressive-fanout reference(https:github.qkg1.toptscircuitcoreblob25595a9988b542334f1b9a7d1a2c083b8796f633testsfixturescreate-am62l-lpddr4-fanout.tsx): 40 20 mm, eight layers, 373-ball CPU, 200-ball RAM, nine DDR buses, 33 signals, and 68 decoupling capacitors. Its placements, layers, skew limits, and per-chip bus exit directions live in a dedicated configuration TSX file. Future positions can add their own TSX files. The page includes PCB panzoom and downloads for SVG, Circuit JSON, and a reproducible TSX source bundle. build:ddr preserves cores staged rendering of DDR fanout followed by fixed decoupling copper. Site assembly includes the DDR pageartifacts and can reuse the existing 72 sensordisplay boards with --from-public. The updated circuit dependencies support the references fanout APIs. As in core, 45 non-DDR processor power-ball connections represent logical membership in unfinished segmented power rails. The build verifies those exact diagnostics and rejects all other circuit errors; the diagnostics remain in the downloadable JSON. Validation: npm run build:ddr npm run assemble-site -- --from-public npm test: 48 passing, including all 33 routed signals and clockDQS skew checks npm run typecheck npm run build:circuits:plan Existing photodiode circuit CLI schematic-placement smoke check Browser verification of header navigation, three dropdowns, rendered PCB, zoomreset, and responsive layout; no browser errors The 72 existing sensordisplay circuits were reused from their checked-in artifacts rather than rerouted.
#13	🐳 Major	⭐⭐⭐	seveibar	Adds Left to the DDR selector with a dedicated TSX configuration. CPU is at (9.5, 0), rotated 180, and RAM is at (-9.616917, -1.81916), rotated 270, on a 54 32 mm eight-layer board. The board is freshly routed from TSX and includes phase boundaries, phase data, and browsable unzipped sources. All nine CPU buses explicitly exit left; all nine RAM buses exit right. The half turn also swaps the topbottom track ordering within each edge. The shared fanout adapter now supports both 90 and 180 layouts while preserving cores paired exits and layers. Winding sorts the normalized regions CPU-first: cores board-space order puts RAM first for Left, which otherwise changes bus ordering and layer assignment. Left retains the proven fanout solver 0.0.54 configuration, both packages powerground fanout, and eight DDR capacitors. The global phase connects all 33 DDR signals on matching layers. The build rejects copper errors, disconnected signals, global vias, or any via outside the fanout regions. Validation: Rebuilt Right, Top, and Left from TSX and reassembled their public artifacts. Left solves 135135 CPU and 143143 RAM connections; all 33 global DDR signals connect, with 327 traces checked and zero copper errors. Regression coverage verifies all nine direction mappings, actual exits facing the other package, matching global layers, no outside-fanout vias, and winding order when regions are reversed. All 58 repository tests, TypeScript, and git diff --check pass. Browser check: selecting Left loads the PCB, updates the dimensions and resource URLs, and opens its TSX source browser. Clean Ubuntu CI(https:github.qkg1.toptscircuitquick-configureactionsruns33779123285) passed all three TSX builds, site assembly, 58 tests, and TypeScript. Vercel preview deployment passed. The regenerated Right and Top PCB SVGs are byte-for-byte unchanged.
#14	🐙 Minor	⭐⭐	seveibar	Adds RAM Below to the DDR selector with a dedicated __bottom.circuit.tsx configuration. CPU is at (0, 9.5), rotated 270, and RAM is at (1.81916, -9.616917), rotation 0, on a 32 54 mm eight-layer board. The generated preview includes all three routing-phase boundaries, phase data, and browsable unzipped sources. All nine CPU buses explicitly exit the bottom edge and all nine RAM buses exit the top edge. The 270 mapping preserves the proven Right references within-edge track ordering, including the differential clock and DQS buses. Shared rotation helpers now support 90, 180, and 270 configurations while core continues to coordinate the solved exit positions and layers. RAM Below runs fanout solver 0.0.54 and includes both packages powerground fanouts plus eight DDR capacitors. Its global phase directly joins all 33 DDR signals on matching layers. The build rejects copper errors, disconnected signals, global vias, or vias outside either fanout. Validation: Rebuilt Right, Top, Left, and RAM Below from TSX and reassembled public artifacts. RAM Below solves 135135 CPU connections and 143143 RAM connections; all 33 global DDR signals connect, with 327 traces checked and zero copper errors. Regression coverage verifies all nine Below directions, 270 winding order, cores paired handoff, actual exits facing the other package, matching global layers, and no vias outside the fanouts. All 63 repository tests, TypeScript, and git diff --check pass. Browser check: selecting RAM Below loads the PCB, updates the 32 54 mm caption and resource URLs, and opens the Bottom TSX source browser. Regenerated Right, Top, and Left PCB SVGs are byte-for-byte unchanged. Clean Ubuntu CI(https:github.qkg1.toptscircuitquick-configureactionsruns33781557678) passed all four TSX builds, site assembly, 63 tests, and TypeScript. Vercel preview deployment also passed.

🐌 Tiny Contributions (1)

PR #	Impact	Contributor	Description
#15	🐌 Tiny	seveibar	Renames the RAM placement from Below to Bottom and hides PCB debug overlays in the generated drawings.

tscircuit/props

PR #	Impact	Rating	Contributor	Description
#723	🐙 Minor	⭐⭐	seveibar	Adds simplify as a supported autorouter preset, allowing cleanup across all traces without a selector and warns if used without reroutetrue.

tscircuit/circuit-to-svg

PR #	Impact	Rating	Contributor	Description
#712	🐙 Minor	⭐⭐	seveibar	Renders display_superscript on both schematic_net_label and schematic_text as a smaller raised suffix, supporting outlined labels in all orientations, groundpower symbols, and inline labels alongside wires.

🐌 Tiny Contributions (1)

PR #	Impact	Contributor	Description
#711	🐌 Tiny	seveibar	Fixes the issue where schematic sheet frames are incorrectly centered at the origin instead of their specified center, ensuring proper rendering of components within the frame.

tscircuit/svg.tscircuit.com

PR #	Impact	Rating	Contributor	Description
#2186	🐙 Minor	⭐⭐	seveibar	Add a show_debug_objects request flag for PCB SVG and PNG output, allowing users to render PCB debug object overlays such as autorouting phase bounds.

tscircuit/docs

PR #	Impact	Rating	Contributor	Description
#865	🐙 Minor	⭐⭐	seveibar	Clarifies the behavior of automatic copper pours and routing guidance, removing references to retired autorouter presets and detailing the functionality of automaticPoursEnabled.

🐌 Tiny Contributions (3)

PR #	Impact	Contributor	Description
#864	🐌 Tiny	seveibar	Replace separate controller and memory previews with a routed two-chip DDR byte-lane example, adding a CircuitPreview showDebugObjects prop and explaining the controller and memory fanout and board-level channel phases.
#862	🐌 Tiny	seveibar	Add a Routing DDR guide covering bus decomposition, opposing package fanouts, layer allocation, tuning room, and end-to-end verification, along with live CircuitPreview examples for controller and memory byte-lane fanout.
#863	🐌 Tiny	seveibar	Clarifies the boundaries for DDR fanout by moving synthetic DDR channel endpoints outside each breakout and relying on Cores implicit breakout points.

tscircuit/high-density-repair02

🐌 Tiny Contributions (1)

PR #	Impact	Contributor	Description
#68	🐌 Tiny	seveibar	Reproduces a visual snapshot of the BGA36 C_BOTTOM pad approach to capture the current bug in the solvers output, without making production changes.

tscircuit/ti

PR #	Impact	Rating	Contributor	Description
#229	🐳 Major	⭐⭐⭐	Abse2001	Summary compose the complete Automotive Window Module from the seven reviewed TI subcircuits add a readable multi-sheet TSX example and checked-in schematic snapshot add the Automotive Window Module preset to the system-block builder with semantic power and data connections preserve subcircuits that own internal schematic sheets and generate correctly scoped descendant traces use native default A4 pages for all smaller circuits, including Watchdog and Vref; retain larger sheets only for Main Supply (ANSI B), the MSP430 reference (500 mm 330 mm), and TIDA-01421 Pinch Detection (430 mm 280 mm) verify sheet dimensions and circuit containment in both the standalone example and builder output, without changing component positions or routing verify nine real schematic sheets and KiCad project export TI reference https:www.ti.comsolutionautomotive-window-module?variantid34360subsystemid24690subsystem-reference-design Generated schematic snapshot !Automotive Window Module schematic sheets(https:github.qkg1.toptscircuittiblobfeatautomotive-window-module-completeexamples__snapshots__AutomotiveWindowModule.circuit-schematic.snap.svg?rawtrue) Verification cd system-block-ui bun test 69 passed, 0 failed cd system-block-ui bun run build bun run format:check visually checked all eight circuit sheets after regenerating the snapshots
#234	🐳 Major	⭐⭐⭐	imrishabh18	Adds functionality to display recommended TI parts with an expandable MCP JSON response, including caching and error handling for recommendations.
#228	🐳 Major	⭐⭐⭐	imrishabh18	Adds a server-only TI Support Intelligence MCP client that fetches and displays TI recommendations in the subcircuit picker, allowing users to see recommended parts alongside local subcircuits.
#225	🐳 Major	⭐⭐⭐	imrishabh18	Add a subcircuit picker modal for selecting TI parts within system blocks, allowing users to replace blocks while preserving compatible connections and providing clear notifications for incompatible links.
#227	🐙 Minor	⭐⭐	imrishabh18	Limits the subcircuit picker to show only subcircuits within the selected blocks category, while excluding the current and non-instantiable subcircuits, and preserving alphabetical order within the matching category.

🐌 Tiny Contributions (7)

PR #	Impact	Contributor	Description
#224	🐌 Tiny	seveibar	Add MSPM33C321A and MSPM33C3219 exports for the 100-pin PZ LQFP package, add MSPM0C1104 package selection for 20-pin DGS VSSOP and 8-pin DSG WSON parts, and introduce reusable Microcontroller_MSPM0G5117 and Microcontroller_MSPM0G5187 basic-application subcircuits with TI-recommended support.
#235	🐌 Tiny	imrishabh18	Removes the block count, automatic power label, and data-link count from the system-block canvas toolbar, along with adjacent divider and unused calculations and styles, while preserving existing controls.
#233	🐌 Tiny	techmannih	Updates the circuit-json-to-altium dependency to a specific commit and refreshes the Bun lockfile for the new Git resolution.
#221	🐌 Tiny	techmannih	Summary replace explicit netlabel elements with named native traces remove legacy manual label positioning helpers and update connectivity assertions refresh only existing affected snapshots and add a guard against reintroducing manual netlabels Validation bun run typecheck focused tests: 20 pass full bun test: 121 pass, 1 pre-existing failure in PowerSupply_WindowModule.test.tsx for missing sheet dimensions existing snapshots updated: 42 modified, 0 added Biome formatting passes for all PR sourcetest files; repository-wide check is blocked only by unrelated untracked files under tmp
#226	🐌 Tiny	techmannih	Fixes the length of the port stems for the LM5050 TVS symbol to align with the symbol body.
#223	🐌 Tiny	techmannih	Fixes Altium exporter to use five-digit schematic fractional coordinates and prevents rendering issues with giant symbol lines and filled polygons in Real View.
#222	🐌 Tiny	techmannih	Updates the circuit-json-to-altium dependency to a specific commit and refreshes the Bun lockfile for the new Git resolution.

tscircuit/matchpack

PR #	Impact	Rating	Contributor	Description
#237	🐙 Minor	⭐⭐	mohan-bee	Fixes misclassification of two-pin crystals as generic loads, preserving crystal circuit alignment in the layout.

🐌 Tiny Contributions (2)

PR #	Impact	Contributor	Description
#240	🐌 Tiny	GokulPandi-M	Reproduces a schematic auto-layout failure where components from adjacent partitions are packed closer than the configured partition gap, causing their rendered annotations to collide.
#236	🐌 Tiny	mohan-bee	Adds a new test and input JSON for reproducing the schematic layout of the board 8822.

tscircuit/circuit-json-to-gerber

PR #	Impact	Rating	Contributor	Description
#159	🐙 Minor	⭐⭐	imrishabh18	Fixes duplicate drill operations in Gerber file exports by deduplicating via drill records based on exact coordinates and drill diameter, ensuring accurate representation of physical vias without unnecessary fallback drills.
#158	🐙 Minor	⭐⭐	imrishabh18	Fixes incorrect drill file generation by prioritizing physical layer spans over deprecated routing endpoints during Gerber file export.
#154	🐙 Minor	⭐⭐	mohan-bee	Fixes the issue of zero-length wire-to-via transitions that create unintended Gerber copper, preventing real gesture-controller short reproductions.

🐌 Tiny Contributions (1)

PR #	Impact	Contributor	Description
#157	🐌 Tiny	Abse2001	Adds regression tests and fixtures for physical-via export without altering existing implementations or introducing new production code.

tscircuit/high-density-repair01

PR #	Impact	Rating	Contributor	Description
#17	🐳 Major	⭐⭐⭐	imrishabh18	Visual reproduction !Bug Report 94 before and after force improvement(https:raw.githubusercontent.comtscircuithigh-density-repair01f29ff705b019dc8a18bd2560aa6fe61124b1f543tests__snapshots__bugreport94-force-crossing.snap.svg) Red is source_trace_108, blue is source_trace_138, and green is neighboring source_trace_99. The left panel is the raw force-pass result, where source_trace_108 crosses source_trace_138. The right panel is the final HighDensityForceImproveSolver result: the original crossing is removed without transferring the overlap to source_trace_99. This image is the committed test artifact from tests__snapshots__bugreport94-force-crossing.snap.svg; the test also asserts the corresponding centerline clearances numerically. Summary fix Bug Report 94 in the actual HighDensityForceImproveSolver detect proper segment-interior crossings left by the guarded force rerun recover a small route corridor from the original topology, aligned to the force result project only newly affected neighboring routes and accept a candidate only when protected pairs stay clear and the local violation count decreases add a focused regression for source_trace_108 against both source_trace_138 and source_trace_99 Root cause The force solver enforced point-to-segment clearance without preserving segment-pair topology. Adjacent points could remain individually valid while two segment interiors swapped sides and crossed. The existing guarded rerun removed the original source_trace_108 source_trace_138 crossing, but its whole-node movement transferred the overlap to source_trace_108 source_trace_99. The output therefore looked improved in the snapshot while the final DRC count remained 6. This change adds a post-rerun acceptance step. It reconstructs only the crossing corridor from the original non-crossing topology, aligns it to the fixed force-result segment, resolves any newly touched neighbor locally, and rejects candidates that restore a protected overlap or fail to reduce the number of violating route pairs. Validation bun test 15 passed, 0 failed bun run typecheck passed upstream format, test, and typecheck CI passed full autorouter Bug Report 94 5 DRC errors, no trace-overlap error involving source_trace_108

tscircuit/implicit-copper-pour-solver

PR #	Impact	Rating	Contributor	Description
#11	🐳 Major	⭐⭐⭐	imrishabh18	Adds a configurable trace clearance with a default of 0.2 mm, expands foreign-trace visibility barriers, checks clearance-aware connectivity across grid-cell boundaries, and updates snapshots and regression coverage.

tscircuit/calculate-cell-boundaries

PR #	Impact	Rating	Contributor	Description
#37	🐳 Major	⭐⭐⭐	mohan-bee	Preserves cell boundaries when preferred margins connect all cells, ensuring that section dividers are maintained even when contents are separate.
#36	🐙 Minor	⭐⭐	mohan-bee	Reproduces the issue of missing dividers when section margins are expanded, providing a test case and SVG snapshot for boundary calculations.

tscircuit/length-matching-solver

PR #	Impact	Rating	Contributor	Description
#60	🐳 Major	⭐⭐⭐	mohan-bee	Motivation Capture the RV1106G2 camera routing failure with the real board post-processing input. Before A 180-degree differential-pair spine crashed without a full-board regression or snapshot. After Adds the captured board fixture, asserts the current crash, and snapshots the complete board state.
#61	🐳 Major	⭐⭐⭐	mohan-bee	Fixes post-processing crash caused by 180-degree spine reversal in differential pair routing.

tscircuit/circuit-json-schematic-placement-analysis

🐌 Tiny Contributions (1)

PR #	Impact	Contributor	Description
#36	🐌 Tiny	mohan-bee	Reproduces a bug where trace-anchored net labels can overlap adjacent net labels without a placement warning.

tscircuit/high-density-a01

PR #	Impact	Rating	Contributor	Description
#99	🐳 Major	⭐⭐⭐	AnasSarkiz	Summary This consolidates the already reviewed native-size solver work from 95 and 96 into main: add A12, an A03-derived mixed-resolution solver with exact endpoint preservation and a final geometry gate add A11 rip-history costs to break recurring rip-and-reroute cycles expose the solver choices in the package benchmarkdebugger tooling keep A01 and A03 defaults unchanged; the new behavior is opt-in through A11A12 This PR intentionally contains only the shared solver foundation. Compatibility work and the subsequent A11 topology-aware scheduling improvement remain focused dependent PRs. Canonical HD30 baseline Dataset: tscircuitdataset-hd300ad7fe36c3da67469a053cfa98f709f751f844b1 Settings: regular Pipeline 9 nodes, Pipeline 9 copper dimensions, original bounds, shuffle seed 0, effort 1, and a 100,000-iteration cap. Solver Valid native solves --- ---: A01 027 A03 027 A11 727 A12 827 A11 A12 union 1227 All counted solves pass exact route-geometry validation at the original bounds. Validation on ac13ef80da71c3998acb5302329b6b704d0470d1 full package: 82 passed, 2 skipped, 0 failed build passed format check passed canonical four-solver HD30 matrix reproduced.

tscircuit/kicad-to-circuit-json

PR #	Impact	Rating	Contributor	Description
#177	🐳 Major	⭐⭐⭐	ShiboSoftwareDev	Summary read schematic wire geometry from the public kicadts Wire.points API and keep KiCad junctions on renderable traces place ports with the selected symbol unitbody-style transform and emit matching source_port records render embedded KiCad symbol primitives, pin namesnumbers, and visible referencevalue fields instead of generic component boxes preserve standalone text, hierarchical sheets and pins, no-connect markers, rectangles, polylines, and arcs distinguish plain KiCad local labels from shaped global labels, while retaining their unique source_net records preserve hierarchical-sheet pin direction markers, readable text orientation, inset placement, and KiCad sheet colors update the HSP USB LED and pic-programmer native-KiCad-vs-converted snapshots Why The importer previously read a nonexistent wire property, placed pins relative to the page origin, combined pins from every unit, and discarded most embedded symbol and top-level schematic graphics. Real schematics therefore lost wires, used generic boxes, showed misplacedduplicated ports, and omitted labels, annotations, grouping graphics, hierarchical sheets, no-connect markers, and visible junctions. The symbol-local transform now follows KiCads Cartesian symbol coordinates without applying a second Y inversion. Hidden KiCad property text stays hidden, while visible pin and instance text is preserved. Local labels no longer render as boxed global arrows, and 180-degree sheet pins remain readable instead of appearing upside down. This PR is stacked on 176 so its diff contains only the conversion fix and its regression coverage. Visual regression Both real-circuit snapshots keep the native KiCad schematic on the left and the converted Circuit JSON schematic on the right. The regressions verify: HSP USB LED: 13 wire traces, 1 junction, 23 sourceschematic ports, real USBpassivepower symbol geometry, and both source grouping rectangles pic-programmer: 131 wire traces, 26 junctions, 182 sourceschematic ports, 10 plain local-label instances backed by 7 unique source nets, the hierarchical sheet and its 4 readable pin markers, 6 no-connect markers, and 8 dashed source drawing paths Verification bun test testsschematic-source-component-links.test.ts testspic-programmer-parity-sch.test.ts bunx tsc --noEmit bun run format:check bun run build
#180	🐙 Minor	⭐⭐	ShiboSoftwareDev	Fixes oversized standalone KiCad board text by using the native font height for rendering, ensuring accurate text size in the conversion to Circuit JSON.

🐌 Tiny Contributions (2)

PR #	Impact	Contributor	Description
#176	🐌 Tiny	ShiboSoftwareDev	Summary link each imported schematic component to the actual source component ID returned by the database insert keep the inferred component type fully typed without an any cast use the real HSP USB LED KiCad schematic instead of the synthetic one-component fixture show both the HSP USB LED and pic-programmer schematic parity snapshots with native KiCad on the left and imported Circuit JSON on the right Why The importer inserted IDs such as source_component_0 but linked schematic components to fabricated IDs such as Device:R_source. Consumers could not resolve those references. Visual regression The existing repository test now runs against nushackershsp-pcb-introsrcusb_led.kicad_sch. Its snapshot shows the native KiCad source on the left and imported Circuit JSON on the right using an optional horizontal layout in the existing labeled stacking helper. The existing pic-programmer schematic parity test now uses the same side-by-side layout and refreshes its Circuit JSON inspection artifacts. Source revision: ad3fbd582e3915b585c453ea202f591720a1f427 (CERN-OHL-P-2.0), SHA-256 425a817f1c236363eefd6ff8cb23365d2641a43d5f1e057191497046dcf20d75. Verification bun run format:check bunx tsc --noEmit bun test testsschematic-source-component-links.test.ts testspic-programmer-parity-sch.test.ts bun run build
#179	🐌 Tiny	ShiboSoftwareDev	Updates the bundled parser to kicadts 0.0.57 to ensure KiCad 10 schematic properties with show_name and do_not_autoplace parse and round-trip correctly.

tscircuit/kicadts

PR #	Impact	Rating	Contributor	Description
#67	🐙 Minor	⭐⭐	ShiboSoftwareDev	Accepts and preserves the show_name and do_not_autoplace children emitted on ordinary schematic properties by KiCad 10, integrating them into Property parsing, construction, accessors, and serialization with round-trip coverage.

tscircuit/dataset-srj32-trace-simplification

PR #	Impact	Rating	Contributor	Description
#1	🐳 Major	⭐⭐⭐	0hmX	Summary expand the generator from Dataset 01 to 15 pinned SRJ source families add dataset selection, bounded workers, per-problem timeouts, and serialized crash-safe writes regenerate the corpus with 296 valid records from 14 represented families add per-source provenancecounts and a manifest writer document generation and add source inventory coverage SRJ13 is supported by the generator but has no committed records because its inputs fail before reaching trace simplification in the winding-breakout stage. Corpus 296 records 7,178 inputoutput traces 390,651 input route points 74,838 output route points SHA-256: b7ee77cc018862647e44ee9e160bf2558caef99781c5ec80f5c0e2d57b8ebb99 Validation bun run check 296 Pipeline 11 replay validations 2 tests, 598 assertions

tscircuit/circuit-json-to-gltf

🐌 Tiny Contributions (1)

PR #	Impact	Contributor	Description
#190	🐌 Tiny	KrishnaX12	Description Downloading the 3D PNG for seveibarusb-c-flashlight places the USB-C connector away from its solder pads. The same connector is positioned correctly in the interactive viewer on docs.tscircuit.com. This PR adds a reproduction test using the Circuit JSON from the published v1.0.0 release and a full-board snapshot that captures the incorrect placement on the current main branch. The exposed pad row behind the connector makes the offset easy to see. No renderer code is changed. The snapshot records the current incorrect output, so the test passes while preserving the bug for the related fix. Fixture Package: seveibarusb-c-flashlight Version: v1.0.0 Release ID: 35fa29c2-6067-4d62-9c97-4b418fb4870f Circuit JSON: distindexcircuit.json 3D model: URL referenced by the published release Reproduction bun test testsreprousb-c-flashlight-origin.test.ts Current 3D PNG output !USB-C connector incorrectly offset in downloaded 3D PNG(https:github.qkg1.topuser-attachmentsassetsaaa3f718-79c4-4d41-be7a-4cd78d24215d) In https:docs.tscircuit.com !USB-C connector correctly positioned in the interactive viewer(https:github.qkg1.topuser-attachmentsassets30918d71-4234-490d-9625-99c36263f473) Validation Reproduction test passes Formatting passes TypeScript passes Snapshot visually inspected fix: 189

tscircuit/altium-to-circuit-json

🐌 Tiny Contributions (1)

PR #	Impact	Contributor	Description
#45	🐌 Tiny	anil08607	Fixes the inability to scroll vertically on the left control panel when content exceeds the viewport height on smaller screens.

Changes by Contributor

tscircuitbot

🐌 Tiny Contributions (240)

PR #	Impact	Description
#4766	🐌 Tiny	Automated package update
#4763	🐌 Tiny	Automated package update
#755	🐌 Tiny	Automated package update
#753	🐌 Tiny	Automated package update
#751	🐌 Tiny	Automated package update
#3639	🐌 Tiny	Updates the tscircuitfanout-solver package from version 0.0.56 to 0.0.57
#3638	🐌 Tiny	Updates the tscircuitfanout-solver package from version 0.0.56 to 0.0.57
#3637	🐌 Tiny	Updates the tscircuitfanout-solver package from version 0.0.55 to 0.0.56
#3635	🐌 Tiny	Updates the tscircuitfanout-solver package from version 0.0.54 to 0.0.55
#3620	🐌 Tiny	Updates the tscircuitfanout-solver package from version 0.0.53 to 0.0.54
#3611	🐌 Tiny	Updates the tscircuitfanout-solver package from version 0.0.52 to 0.0.53 in the package.json file.
#3607	🐌 Tiny	Updates the tscircuitfanout-solver package from version 0.0.49 to 0.0.52
#3606	🐌 Tiny	Updates the tscircuitfanout-solver package from version 0.0.49 to 0.0.52
#3592	🐌 Tiny	Updates the tscircuitchecks package from version 0.0.179 to 0.0.180 in the package.json file.
#3591	🐌 Tiny	Updates the version of the tscircuitchecks package from 0.0.179 to 0.0.180 in package.json
#3579	🐌 Tiny	Updates the tscircuitfanout-solver package from version 0.0.48 to 0.0.49
#3588	🐌 Tiny	Updates the version of the tscircuitchecks package from 0.0.178 to 0.0.179 in package.json
#3578	🐌 Tiny	Updates the tscircuitfanout-solver package from version 0.0.47 to 0.0.48
#4780	🐌 Tiny	Updates the tscircuitrunframe package from version 0.0.2658 to 0.0.2659
#4779	🐌 Tiny	Automated package update
#4778	🐌 Tiny	Automated package update
#4777	🐌 Tiny	Updates the tscircuiteval package from version 0.0.1345 to 0.0.1349 in the package.json file.
#4776	🐌 Tiny	Updates the tscircuitrunframe package version from 0.0.2656 to 0.0.2657 in package.json
#4774	🐌 Tiny	Automated package update
#4772	🐌 Tiny	Updates the tscircuitrunframe package from version 0.0.2653 to 0.0.2655
#4763	🐌 Tiny	Updates the tscircuitrunframe package from version 0.0.2646 to 0.0.2649
#4769	🐌 Tiny	Updates the tscircuiteval package version from 0.0.1343 to 0.0.1345 in package.json
#4764	🐌 Tiny	Updates the tscircuitrunframe package from version 0.0.2649 to 0.0.2650
#4768	🐌 Tiny	Updates the tscircuitrunframe package version from 0.0.2652 to 0.0.2653
#4767	🐌 Tiny	Automated package update for tscircuitrunframe from version 0.0.2651 to 0.0.2652
#4766	🐌 Tiny	Updates the tscircuitrunframe package from version 0.0.2650 to 0.0.2651
#4760	🐌 Tiny	Updates the tscircuiteval package from version 0.0.1342 to 0.0.1343
#4758	🐌 Tiny	Updates the tscircuiteval package to version 0.0.1342
#4755	🐌 Tiny	Updates the tscircuitrunframe package from version 0.0.2642 to 0.0.2645
#4757	🐌 Tiny	Updates the tscircuitrunframe package from version 0.0.2645 to 0.0.2646
#4743	🐌 Tiny	Updates the tscircuiteval package from version 0.0.1334 to 0.0.1335
#4742	🐌 Tiny	Updates the tscircuitrunframe package from version 0.0.2638 to 0.0.2639
#4752	🐌 Tiny	Updates the tscircuiteval package from version 0.0.1336 to 0.0.1338
#4746	🐌 Tiny	Automated package update
#4745	🐌 Tiny	Automated package update
#4744	🐌 Tiny	Updates the tscircuiteval package from version 0.0.1335 to 0.0.1336
#4741	🐌 Tiny	Updates the tscircuiteval package from version 0.0.1327 to 0.0.1334
#4740	🐌 Tiny	Updates the tscircuitrunframe package from version 0.0.2637 to 0.0.2638
#4738	🐌 Tiny	Updates the tscircuitrunframe package from version 0.0.2636 to 0.0.2637
#4736	🐌 Tiny	Updates the tscircuitrunframe package from version 0.0.2635 to 0.0.2636
#4733	🐌 Tiny	Automated package update
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#1063	🐌 Tiny	Adds a snapshot-only regression test and debugger page for the attached JSON solver input.
#1037	🐌 Tiny	Adds a snapshot-only regression test and debugger page for the attached JSON solver input.
#1035	🐌 Tiny	Adds a snapshot-only regression test and debugger page for the attached JSON solver input.
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rushabhcodes

PRs #	Impact	Rating	Description
#86	🐳 Major	⭐⭐⭐	Fixes the omission of oval plated holes in copper pour calculations, ensuring proper clearance and thermal relief for designs using oval plated holes.
#540	🐙 Minor	⭐⭐	Fixes incorrect CAD component size calculation by deriving dimensions from the models bounding box instead of PCB footprint dimensions, ensuring accurate rendering of components.
#3594	🐙 Minor	⭐⭐	Refines schematic sheet warning assertions to ensure tests only check for relevant warnings, preventing false negatives due to unrelated warnings.

🐌 Tiny Contributions (7)

PR #	Impact	Description
#4765	🐌 Tiny	Fixes copper pour solver to respect clearance around oval plated holes, preventing different-net pours from extending into required pad clearances.
#543	🐌 Tiny	Fixes rendering of the C7519 schematic by preserving the fill color and visibility of protection diodes, correcting a bug where the fill color was incorrectly displayed as the outline color.
#542	🐌 Tiny	Reproduces a bug where the C7519 schematic renders incorrectly as a solid red rectangle instead of the expected design, providing a baseline for future fixes.
#539	🐌 Tiny	Adds a regression test for the C165948 CAD footprint size mismatch issue, recording the incorrect emitted CAD size metadata and providing a 3D snapshot for visibility.
#534	🐌 Tiny	Reproduces a bug where HTML-encoded pin aliases from EasyEDA are incorrectly processed, leading to invalid pin labels in generated components.
#3623	🐌 Tiny	Refreshes the AM62L-to-LPDDR4 two-bus BGA fanout PCB snapshot to align the expected route geometry with the deterministic output from the fanout solver version 0.0.54, addressing a CI failure due to stale SVG geometry.
#3593	🐌 Tiny	Updates the tscircuitcopper-pour-solver dependency to version 0.0.52, enabling proper copper-pour handling for oval plated holes in PCB designs.

MustafaMulla29

PRs #	Impact	Rating	Description
#745	🐳 Major	⭐⭐⭐	Add an optional pcb_component_id to the shared PCB cutout schema to identify owning PCB components for footprint-defined cutouts, enabling better overlap checks.
#3628	🐳 Major	⭐⭐⭐	Propagates the owning pcb_component_id to rectangular, circular, and polygon footprint cutouts and adds a focused regression test for a cutout declared inside a chip footprint.
#1054	🐳 Major	⭐⭐⭐	Fixes unnecessary doglegs in schematic traces by refining corner pin direction handling and improving routing algorithms to minimize turns and collisions with labels.
#1020	🐳 Major	⭐⭐⭐	Aligns adjacent same-side pin exits onto neighboring pin rows, aligns degree-two buses between perpendicular endpointload traces, and preserves generated connector junctions while validating candidates against various criteria.
#1013	🐳 Major	⭐⭐⭐	Reroutes component-to-component traces to avoid crossings with generated net-label connectors, ensuring cleaner routing and preserving valid label-to-label crossings.
#259	🐙 Minor	⭐⭐	Fixes placement errors for components over their own footprint cutouts by ignoring such errors during validation and adds a regression test to ensure correct behavior.
#257	🐙 Minor	⭐⭐	Fixes clearance geometry calculations for plated-hole pill and oval copper pads to ensure accurate DRC checks without false errors.
#1052	🐙 Minor	⭐⭐	Prevents anchored label connectors from creating strict perpendicular crossings with unrelated traces, ensuring safer label placements in schematic designs.

🐌 Tiny Contributions (9)

PR #	Impact	Description
#4762	🐌 Tiny	Updates the versions of core and eval dependencies in the package.json file.
#3649	🐌 Tiny	Updates the version of the schematic-trace-solver dependency from 0.0.178 to 0.0.183 in package.json
#3644	🐌 Tiny	Bumps tscircuitchecks from 0.0.181 to 0.0.182, consuming the owned-footprint-cutout placement fix and outline-keepout compatibility fix from a related pull request.
#3625	🐌 Tiny	Updates the version of the tscircuitchecks dependency from 0.0.180 to 0.0.181 in the package.json file.
#3582	🐌 Tiny	Updates the tscircuitschematic-trace-solver dependency from version 0.0.175 to 0.0.178, including connector-crossing reroute improvements from a related pull request.
#256	🐌 Tiny	Reproduces the two 0 mm pad-clearance errors from the unmodified generated component EC10E1220505 in a regression test, including a PCB SVG snapshot with error visualization enabled.
#1050	🐌 Tiny	Add a focused schematic trace reproduction for the two mouse switches, capturing solver input and snapshotting the unnecessary horizontal jog in the vertical GND trunk.
#1047	🐌 Tiny	Reproduces an unnecessary dogleg in the RF1 trace between two nominally aligned inductors, providing a focused test case without implementing solver changes.
#1044	🐌 Tiny	Add an isolated reproduction of the capacitor-side VBAT label crossing the long CHG_STAT trace, using the exact InputProblem emitted by tscircuitcore 0.0.1829 at commit b761dc8, while retaining specific components and adding a focused solver SVG snapshot.

hrithik18k

PRs #	Impact	Rating	Description
#4729	🐳 Major	⭐⭐⭐	Fixes schematic downloads to include all sheets in multi-sheet projects instead of just the firstdefault sheet.
#748	🐙 Minor	⭐⭐	Adds structured text runs for schematic pin labels, allowing individual segments to be marked as overlined.

🐌 Tiny Contributions (5)

PR #	Impact	Description
#121	🐌 Tiny	Fixes rendering of Altium schematic arcs to correctly handle angles crossing zero degrees, ensuring accurate representation of wrapped arcs.
#117	🐌 Tiny	Reproduces the rendering difference of a magnetic-core inductor in the schematic compared to Altium Designer without changing renderer behavior.
#113	🐌 Tiny	Fixes the issue where the renderer uses incorrect dimensions for predefined Altium sheets, ensuring complete schematics are displayed according to selected sheet sizes.
#111	🐌 Tiny	Reproduces a valid PowerSupply schematic appearing blank due to content being clipped outside the page boundary.
#106	🐌 Tiny	Pins altiumts to a specific commit to validate the predefined Altium sheet-sizing fix in the converter before merging another PR, ensuring all converter tests pass with the corrected dimensions.

seveibar

PRs #	Impact	Rating	Description
#3655	🐳 Major	⭐⭐⭐	Exposes autorouter cache decisions and metadata during local autorouting lifecycle events, ensuring that routing experiments are accurate and not misled by stale routes.
#3581	🐳 Major	⭐⭐⭐	Add a new autorouting phase that simplifies existing PCB traces and integrates with the autorouting pipeline, enhancing routing efficiency.
#4748	🐳 Major	⭐⭐⭐	Updates the editor URL when a workspace file is selected, preserving existing query parameters and clearing stale line selections, while adding a browser regression test for file selection URL sync.
#4735	🐳 Major	⭐⭐⭐	Provides detailed error messages for avatar upload failures, including server rejection reasons and network issues, improving user guidance during upload attempts.
#4734	🐳 Major	⭐⭐⭐	Fixes the issue where the editor opens lockfiles by default instead of the intended circuit entrypoint files, ensuring that only eligible files are selected for editing.
#2402	🐳 Major	⭐⭐⭐	Fixes via span DRC evaluation to include all layers in the reference DRC, ensuring accurate collision detection and preserving staged repairs during autorouting.
#2407	🐳 Major	⭐⭐⭐	Add --dataset srj33 to the benchmark and run-sample loaders, and a Cosmos benchmark fixture for all 31 original bug-report inputs from dataset-srj33-drc-failures.
#2399	🐳 Major	⭐⭐⭐	Fixes autorouting issues by preserving connected-pad boundaries during Pipeline9 repair, preventing backwards kinks in traces entering their own pads.
#2393	🐳 Major	⭐⭐⭐	Adds a collision-checked vertex cleanup pass to Pipeline11s path simplifier, reducing redundant vertices and improving route quality on the RP2040 motor controller.
#2390	🐳 Major	⭐⭐⭐	Fixes autorouting failure by excluding obstacles connected to a route in the Pipeline9 repair process, ensuring that the repair solver does not displace traces away from their own pads.
#2349	🐳 Major	⭐⭐⭐	Reuses static connectivity during DRC repair in Pipeline9 to improve performance and reduce timeouts.
#2370	🐳 Major	⭐⭐⭐	Fixes the autorouting progress reporting for Pipeline 7 and Pipeline 9, ensuring accurate progress updates during routing operations.
#2335	🐳 Major	⭐⭐⭐	Summary add numbered AutoroutingPipelineSolver11_Simplification, a cleanup-only pipeline for existing SimpleRouteJson.traces use the conventional BasePipelineSolver definition with explicit prepare, simplify, apply, and DRC-validation stages; the outer pipeline does not override _step() keep stage work incremental: one input trace, one wrapped solver step, one output trace, or one validation pass per _step() preserve variable-width traces exactly and include them as immutable collision geometry while simplifying constant-width traces opt Pipeline 11 into clearance checks that use the actual currentneighbor trace widths and a matching spatial-search margin, without changing established pipeline behavior preserve trace IDs, connection metadata, endpoints, terminal vias, and terminal PCB-port metadata without routing missing SRJ connections Why The simplify autorouting phase needs a dedicated local pipeline for users who want to improve traces that are already routed. Reusing the normal autorouting pipeline would solve SRJ connections again instead of limiting the work to post-route cleanup. The cleanup solvers currently use one traceThickness per high-density route. Sending a variable-width SRJ trace through that representation collapsed every segment to one arbitrary width and created DRC violations. Pipeline 11 now makes that capability boundary explicit: constant-width routes are simplified, while variable-width routes retain their exact copper geometry and still block unsafe shortcuts. Companion props PR: https:github.qkg1.toptscircuitpropspull723 Real-board visual snapshot The fixture was captured from the board and MCU autorouting events produced by imrishabh18rp2040-motor-controller(https:tscircuit.comimrishabh18rp2040-motor-controllerfiles) at tscircuitrp2040-motor-controllerb4560e5(https:github.qkg1.toptscircuitrp2040-motor-controllercommitb4560e5). Pipeline 11 preserves all 148 traces and every input width set, including 30 exact variable-width routes. It reduces route points from 1,829 to 1,763 and vias from 150 to 73, while exact relaxed DRC remains 0 0. !RP2040 motor controller before and after Pipeline 11 simplification(https:raw.githubusercontent.comtscircuittscircuit-autorouterfeatsimplification-pipelinetests__snapshots__pipeline11-simplification-rp2040-motor-controller-visual-rp2040-motor-controller-before-after.snap.svg) Validation bun run build bunx tsc --noEmit focused Pipeline 11 suite: 4 tests passed Pipeline 9 reference-clean exact-output regression test passed real-board test: all width sets preserved, 30 variable-width routes exact, exact relaxed DRC 0 0 visual snapshot regenerated, rendered to PNG, and inspected git diff --check GitHub CI: all 9 test shards, build, type-check, format-check, added-code check, and Vercel checks passed
#99	🐳 Major	⭐⭐⭐	Changes the via span API to exclusively use from_layer and to_layer, removing the optional layers field and ensuring DRC and Circuit JSON conversion derive the inclusive board-layer span from required endpoints.
#96	🐳 Major	⭐⭐⭐	Normalizes DRC checks for vias to include all layers in their span, ensuring accurate collision detection across multiple layers without altering input geometry.
#92	🐳 Major	⭐⭐⭐	Fixes DRC to ensure that vias are validated across their physical layer spans, preventing routing errors that could short copper on intermediate layers.
#149	🐳 Major	⭐⭐⭐	Summary add bounded local dogbone repair and displaced-via routing for constrained differential pairs add adaptive top-edge plane candidate selection with causal reservation refinement add a dataset31 reductiondebug script plus reduced and full SVG regression snapshots improve the dataset31 benchmark from 112 to 212 without regressing the existing left-center pass Benchmark Command: .benchmark.sh --concurrency 4 --sample-timeout-seconds 120 solved 212 02-top-center: 135135, validated, 86.61s 11-left-center: 135135, validated, 15.43s remaining 10 samples: 120s timeout Verification bun test: 152 pass, 0 fail bun run typecheck bun run format:check git diff --check originmain focused reduced snapshot test after generated SVG whitespace cleanup
#141	🐳 Major	⭐⭐⭐	AM62L progressive routing can stall after the fanout-solver update: the initial dense route strands a signal, then repeatedly searches winding paths in a synchronous fallback that prevents Buns test timeout from firing. Core CI hits its 15-minute job limit. Retry coordinated routing before the broad fallback, cache A edge-clearance checks per terminal, and retain ordinary dogbone candidates when automatically matched sites fail. This restores the complete progressive route and one via per connection in the two-bus DRAM case. Route both top-facing layouts with their original timing constraints: Repro 04: route all 135 connections and plane drops before length tuning. Its test no longer removes differential pairs or skew limits. Dataset-fanout31 sample 02-top-center: add the exact capture and a debugger sample with explicit plane reservation hints. Route all 135 connections with 135 through-vias, keeping all original geometry, differential pairs, bus skew limits, and 102 plane terminations. The centered case also requires consistent clearance handling when a winding path leaves its own source pad, corner-aware boundary vias, and joint selection of plane routes when a greedy choice blocks another drop. Enumerate singleton plane candidates once instead of repeatedly regenerating their prefixes. For length matching, revisit excessive detours against completed copper and allow a differential pairs outer lane to move aside before tuning its mate. Searches retain bounded attempts, and complete copper is revalidated before accepting a result. Validation: Top-center regression: 135 connections, 135 through-vias, full routed-copper DRC and original timing constraints pass; 34.7 seconds locally on Bun 1.4.0 and 101.0 seconds in CI. Includes SVG snapshot and capture generator. Constrained Repro 04 passes with its existing snapshot in 7.5 seconds locally and 24.4 seconds in CI, previously 36.2 seconds locally. RAM-left full solve retains its snapshot. Progressive capture passes full DRC with its existing snapshot. Configured corner routing is isolated so the ordinary progressive fanout remains identical to the previously passing output. Typecheck and formatting pass. Single-pass enumeration reproduces all 136 previously captured plane candidates exactly and in order. Earlier Bun CPU profiles of the initial timeout fix reduced the isolated solve from 11.6 to 5.3 seconds with collision caching alone; the published 0.0.51 case was still searching at 30 seconds. Those measurements precede the additional top-facing fixes. Final solver commit 9da1d4c passes all eight test shards, typecheck, formatting, and Vercel. Core commit 40ba64e also passes all ten test shards, typecheck, formatting, smoke test, and Vercel with the final pin. Core dependency update: https:github.qkg1.toptscircuitcorepull3605
#138	🐳 Major	⭐⭐⭐	Summary Route all 135135 AM62L fanout connections in the RAM-left 11-left-center sample from dataset-fanout31-am62l(https:github.qkg1.toptscircuitdataset-fanout31-am62lblob8c73befb36b125c84651c07454a9b940b3c6500asamples11-left-center.tsx), with no validation issues. The complete case takes about 46 seconds locally on the first layer assignment. The captured input is unchanged: all 573 pad obstacles, 102 plane drops, nine DDR signal buses, three differential pairs, and original clearance and length-skew constraints are retained. The upstream sample contains no decoupling capacitors. Scope: AM62L fanout only; this does not complete the RAM fanout or inter-chip DDR routing. Routing changes Align the fine winding grid to the pad lattice to find narrow inter-via channels, and add bounded blocked-terminal route-order retries. Coordinate dogbone sites and avoid reserving corner-bus vias inside a neighboring wide buss source field. Let an embedded singleton such as RESET escape on its source layer, then use one via near the boundary to reach its assigned layer. Match plane sites against the actual routed copper, retaining provisional sites when possible during length matching. Preserve the existing explicitly configured dense-routing path and small-bus ordering. Reproduction and visual coverage Add Dataset 08 with the exact upstream input, a pinned TSXcore capture script, and a timeout-bounded diagnostic CLI. Add input, BYTE1, planes-plus-address, and full-solve SVG regression tests using solver.visualize(). Refresh two existing SoC routing snapshots for the new valid route geometry; the prior top-edge repro keeps its existing snapshot. Full solved SVG(https:github.qkg1.toptscircuitfanout-solverblobtestdataset-fanout31-ram-lefttests__snapshots__fanout31-am62l-left-solved.snap.svg) sh bun scriptssolve-fanout31-left.ts --timeout-ms 120000 --max-layer-combinations 1 --output tmpfanout31-left Validation bun test: 136 passed, 0 failed, across 95 files (348 seconds). bun run typecheck: passed. bun run format:check: passed; oversized-fixture warnings only. bun run build:site: passed. The existing parallel CI test discovery includes the new tests automatically.
#134	🐳 Major	⭐⭐⭐	Summary make component dogbone matching account for full-board obstacles and already-routed vias reserve selected dense plane drops before boundary buses and solve the remaining constrained plane routes with a bounded compatibility search add a binary-reduction debug harness plus the committed TSX generator input add a solved 135-connection solver.visualize() SVG regression snapshot Verification bunx tsc --noEmit bunx biome check ... 9 focused routing tests pass, including all 135 connections in the snapshot regression full captured DDR skew run: 111111 buses, 135135 connections, 0 failed buses
#129	🐳 Major	⭐⭐⭐	Summary add a Cosmos debugger repro for the AM62L nine-bus top-edge breakout failure commit the RAM-above circuit source in scriptsgenerate-reprogenerate-repro04.tsx render that TSX with tscircuitcore using RootCircuit.renderUntilSettled() override the SOC_FANOUT algorithmFn to capture the real fanout-solver input and return a completed no-op autorouter regenerate the committed inputSrj, options fixture without manually rotating or redistributing points retain 135 connections, 589 phase obstacles, eight layers, nine DDR signal buses, 102 plane-drop buses, and three differential pairs verify that all 33 downstream breakout points are on the top boundary snapshot getSvgFromGraphicsObject(solver.visualize()) so the complete RAM-above input geometry and top-edge targets are visually reviewed The generator dependency workspace keeps the current core rendering stack separate from fanout-solvers pinned runtime capacity-autorouter version. Run it with bun run generate:repro04. Current behavior The captured circuit is the AM62L failure case: the solver is unable to complete the 135-connection breakout. The Cosmos page exposes the full solver search for inspection. Verification bun run generate:repro04 (deterministic SHA-256 across repeated runs) bun run typecheck bun test testsam62l-top-edge-breakout-repro.test.ts bun test with the repository-local Bun 1.3.2 (128 pass, 0 fail before the visual assertion was added) bun run build:site git diff --check CI note Format, type-check, Vercel, and the new AM62L repro test pass. The Bun 1.4 CI test job reports an existing SVG snapshot mismatch in am62l-lpddr4-progressive-through-all-dram-repro.test.ts; the same mismatch occurred on this PR before the generator and AM62L visualization commits, while that snapshot passes locally under Bun 1.3.2.
#131	🐳 Major	⭐⭐⭐	Summary move candidate-layer probing out of the constructor and expose assignment and grouped-beam work as active subsolvers break dense through-all routing into visible dense-routing and boundary-bus subsolvers advance via-minimal winding A in bounded 5,000-state batches, with route-order, connection, batch, and expanded-state progress in solver stats give every active work solver a phase-aware visualize() view; boundary routing renders the current grid, frontier, expanded states, active via, and best path render adaptive single-layer progress while obstacle nodes are classified, the flow network is built and augmented, and routes are extracted preserve the synchronous routing APIs by consuming the same incremental generators to completion without constructing debug graphics batch single-layer adaptive grid, terminal, graph, and max-flow work across steps Bus-atomic routing, scoring, and accepted final geometry remain unchanged. Repro03 Before the split, one repro03 step() spent about 17.4 seconds routing all three dense boundary buses. It is now 432 observable iterations, including 307 boundary-search steps. A measured full solve completed in 19.7 seconds with a 182 ms maximum step and a 177 ms maximum boundary-search step while live visualization state was enabled. The active debugger chain during the hotspot is: FanoutAssignmentSolver DenseMixedTerminationSolver BoundaryBusRoutingSolver Successive calls to visualize() during that boundary subsolver now show the A frontier and newly expanded states changing between batches. Testing bun run typecheck bun test on Bun 1.3.2: 129 passed, 0 failed focused repro03 incremental-step and live-visualization regression adaptive single-layer live-visualization regression existing repro03 126-connection routing and DRC regression bun run format:check git diff --check CI note The hosted Bun 1.4 test job reaches 124 passing tests, including both repro03 tests, but the pre-existing nine-bus DRAM SVG snapshot mismatch also reproduces on current main; the workflow then exceeds its five-minute timeout. Baseline run: https:github.qkg1.toptscircuitfanout-solveractionsruns33295395301
#12	🐳 Major	⭐⭐⭐	Top now rebuilds from TSX with all 33 DDR signals connected through the CPU and RAM fanouts. There are zero vias between the fanouts, and every Top via pad is contained in a fanout region. The checked-in Top preview is freshly generated and shows all three routing-phase boundaries. The layout uses the working Right reference topology rotated 90: the CPU is at (0, -9.5), rotated 90, and RAM is at (-1.81916, 9.616917), rotated 180. This changes the earlier dataset layouts CPU orientation. Each position retains a separate TSX configuration. Top includes both packages powerground fanout and eight DDR capacitors; Right additionally includes the references 60 direct processor decouplers. Both Top fanouts explicitly run fanout solver 0.0.54 through cores fanout preset. The adapter preserves cores paired exit coordinates, layers, completed-footprint keepouts, and prior copper. Winding and fanout planning run in the horizontal reference frame and return their results in board coordinates. This handles windings orientation-dependent ordering; CPU coordinates are normalized to 12 decimals while RAM retains native rotation precision because the current solvers tied track ordering is numerically sensitive. The global phase joins matching exits directly and rejects layer mismatches or copper errors. Core 0.0.1830 is pinned with the small unreleased presethandoff patch from tscircuitcore3610. The patch, lockfile, TSX, and build scripts are available in the unzipped source browser. No saved SVG or circuit JSON is used as a routing input. Both positions also expose captured routing-phase data, including the routed traces. Validation: Rebuilt both configurations from TSX with npm run build:ddr, then assembled the actual public previews. Top: CPU 135135 connections, RAM 143143, all 33 global DDR signals connected, 327 PCB traces checked, zero copper errors, and zero vias outside fanouts. Ran the exact core regression testsreprosrepro-am62l-lpddr4-progressive-fanout.test.tsx with solver 0.0.54: 1 pass, 11,483 assertions, including its existing snapshot without updating it. The initial Right rebuild using its original dependency set also reproduced the previously checked-in SVG byte for byte. All 53 repository tests, TypeScript, and git diff --check pass. Regression checks cover coordinated exits, winding order under rotation, exported phase copper, physical DDR connectivity, and rejection of an outside-fanout via. Clean Ubuntu CI run(https:github.qkg1.toptscircuitquick-configureactionsruns33769713673) passed installation, both TSX builds, site assembly, all tests, and TypeScript. The new workflow rebuilds both boards before testing, so stale preview files cannot hide a solver failure. Vercel preview deployment also passed. Visually inspected the generated PCB SVG. In-app browser navigation was blocked by an automatic approval-review service error (404).
#11	🐳 Major	⭐⭐⭐	Adds a DDR Breakouts page at ddr-breakouts, reachable from the header alongside Sensors Displays. The three dropdowns offer AM62L, MT53E1G16D1ZW (LPDDR4), and RAM Position. Right is implemented; Top, Left, and Bottom are visible but disabled. The Right board ports cores progressive-fanout reference(https:github.qkg1.toptscircuitcoreblob25595a9988b542334f1b9a7d1a2c083b8796f633testsfixturescreate-am62l-lpddr4-fanout.tsx): 40 20 mm, eight layers, 373-ball CPU, 200-ball RAM, nine DDR buses, 33 signals, and 68 decoupling capacitors. Its placements, layers, skew limits, and per-chip bus exit directions live in a dedicated configuration TSX file. Future positions can add their own TSX files. The page includes PCB panzoom and downloads for SVG, Circuit JSON, and a reproducible TSX source bundle. build:ddr preserves cores staged rendering of DDR fanout followed by fixed decoupling copper. Site assembly includes the DDR pageartifacts and can reuse the existing 72 sensordisplay boards with --from-public. The updated circuit dependencies support the references fanout APIs. As in core, 45 non-DDR processor power-ball connections represent logical membership in unfinished segmented power rails. The build verifies those exact diagnostics and rejects all other circuit errors; the diagnostics remain in the downloadable JSON. Validation: npm run build:ddr npm run assemble-site -- --from-public npm test: 48 passing, including all 33 routed signals and clockDQS skew checks npm run typecheck npm run build:circuits:plan Existing photodiode circuit CLI schematic-placement smoke check Browser verification of header navigation, three dropdowns, rendered PCB, zoomreset, and responsive layout; no browser errors The 72 existing sensordisplay circuits were reused from their checked-in artifacts rather than rerouted.
#13	🐳 Major	⭐⭐⭐	Adds Left to the DDR selector with a dedicated TSX configuration. CPU is at (9.5, 0), rotated 180, and RAM is at (-9.616917, -1.81916), rotated 270, on a 54 32 mm eight-layer board. The board is freshly routed from TSX and includes phase boundaries, phase data, and browsable unzipped sources. All nine CPU buses explicitly exit left; all nine RAM buses exit right. The half turn also swaps the topbottom track ordering within each edge. The shared fanout adapter now supports both 90 and 180 layouts while preserving cores paired exits and layers. Winding sorts the normalized regions CPU-first: cores board-space order puts RAM first for Left, which otherwise changes bus ordering and layer assignment. Left retains the proven fanout solver 0.0.54 configuration, both packages powerground fanout, and eight DDR capacitors. The global phase connects all 33 DDR signals on matching layers. The build rejects copper errors, disconnected signals, global vias, or any via outside the fanout regions. Validation: Rebuilt Right, Top, and Left from TSX and reassembled their public artifacts. Left solves 135135 CPU and 143143 RAM connections; all 33 global DDR signals connect, with 327 traces checked and zero copper errors. Regression coverage verifies all nine direction mappings, actual exits facing the other package, matching global layers, no outside-fanout vias, and winding order when regions are reversed. All 58 repository tests, TypeScript, and git diff --check pass. Browser check: selecting Left loads the PCB, updates the dimensions and resource URLs, and opens its TSX source browser. Clean Ubuntu CI(https:github.qkg1.toptscircuitquick-configureactionsruns33779123285) passed all three TSX builds, site assembly, 58 tests, and TypeScript. Vercel preview deployment passed. The regenerated Right and Top PCB SVGs are byte-for-byte unchanged.
#754	🐙 Minor	⭐⭐	Adds optional display_superscript: string to schematic text for inline net labels, allowing for display-only superscript suffixes while preserving original text and source_trace_id.
#750	🐙 Minor	⭐⭐	Adds optional display_superscript: string to schematic net labels, allowing for display-only superscript suffixes without changing net identity.
#749	🐙 Minor	⭐⭐	Adds source_confusing_net_name_warning for electrically disconnected source nets that share a name, such as separate GND nets in sibling subcircuits.
#723	🐙 Minor	⭐⭐	Adds simplify as a supported autorouter preset, allowing cleanup across all traces without a selector and warns if used without reroutetrue.
#3660	🐙 Minor	⭐⭐	Populates display_superscript when a name is displayed on more than one source electrical network, ensuring disconnected GND nets in sibling subcircuits render as GND and GND, while connected copies share one suffix and unambiguous names have none.
#3650	🐙 Minor	⭐⭐	Add fabrication notes for internally connected pads, including a path and label, while preserving component properties and excluding solder jumpers.
#712	🐙 Minor	⭐⭐	Renders display_superscript on both schematic_net_label and schematic_text as a smaller raised suffix, supporting outlined labels in all orientations, groundpower symbols, and inline labels alongside wires.
#4605	🐙 Minor	⭐⭐	Shortens cache keys in autorouter logs for improved readability while retaining full cache keys in artifacts.
#4604	🐙 Minor	⭐⭐	Adds detailed autorouter execution metadata including cache status and solver information to diagnostics and board metadata files.
#4590	🐙 Minor	⭐⭐	Serializes concurrent tsci add invocations to prevent overlapping package-manager processes that can race on package.json, lockfiles, and native dependency installation.
#2186	🐙 Minor	⭐⭐	Add a show_debug_objects request flag for PCB SVG and PNG output, allowing users to render PCB debug object overlays such as autorouting phase bounds.
#865	🐙 Minor	⭐⭐	Clarifies the behavior of automatic copper pours and routing guidance, removing references to retired autorouter presets and detailing the functionality of automaticPoursEnabled.
#53	🐙 Minor	⭐⭐	Fixes truncation of bitmap legend labels by implementing glyph-width-aware fitting based on available legend row width, ensuring full labels are displayed when they fit and adding an ellipsis only at the right edge.
#150	🐙 Minor	⭐⭐	Fixes routing failure in browser Web Workers due to the absence of Nodes process global, ensuring debug flags are accessible without crashing.
#144	🐙 Minor	⭐⭐	Summary Make .benchmark.sh, bun run benchmark, and the Blacksmith benchmark workflow run only the 12 directional AM62L cases from tscircuitdataset-fanout31-am62l. Reject other dataset selections. Capture the exact inputs from the pinned upstream TSXcore sample factories before timing, save them under benchmark-resultsinputs, and benchmark this checkouts solver. Retain all 135 connections, 573 pad obstacles, 111 buses, and the original routing constraints. Show only dataset 31 totals and per-sample results in reports and PR comments. Record the dataset revision, reject legacymixed-dataset reports, and include captured inputs in the CI artifact. Remove the legacy SRJ19SRJ29 benchmark scripts and obsolete benchmark workflows. Keep all regression datasetstests and solver code unchanged. Use a frozen lockfile in the benchmark workflow and update the documentation. Verification 8 focused benchmark tests pass (245 assertions), covering all 12 upstream captures, input preservation, CLIreport output, dataset selection, validation, process isolation, and PR authorization. The freshly captured 11-left-center input and solver options exactly match the existing fixture. A normal-deadline RAM-left benchmark solves and validates 135135 connections (56.01 seconds locally). An all-12-case smoke run with an intentionally short 2-second deadline confirms complete execution and reporting; those timeout results are not a performance baseline. Typecheck, formatting, workflow lint, frozen-lockfile installation, and diff checks pass. Formatting retains three existing oversized-fixture warnings. The trusted benchmark comment renderer changes after this PR is merged into the default branch.
#14	🐙 Minor	⭐⭐	Adds RAM Below to the DDR selector with a dedicated __bottom.circuit.tsx configuration. CPU is at (0, 9.5), rotated 270, and RAM is at (1.81916, -9.616917), rotation 0, on a 32 54 mm eight-layer board. The generated preview includes all three routing-phase boundaries, phase data, and browsable unzipped sources. All nine CPU buses explicitly exit the bottom edge and all nine RAM buses exit the top edge. The 270 mapping preserves the proven Right references within-edge track ordering, including the differential clock and DQS buses. Shared rotation helpers now support 90, 180, and 270 configurations while core continues to coordinate the solved exit positions and layers. RAM Below runs fanout solver 0.0.54 and includes both packages powerground fanouts plus eight DDR capacitors. Its global phase directly joins all 33 DDR signals on matching layers. The build rejects copper errors, disconnected signals, global vias, or vias outside either fanout. Validation: Rebuilt Right, Top, Left, and RAM Below from TSX and reassembled public artifacts. RAM Below solves 135135 CPU connections and 143143 RAM connections; all 33 global DDR signals connect, with 327 traces checked and zero copper errors. Regression coverage verifies all nine Below directions, 270 winding order, cores paired handoff, actual exits facing the other package, matching global layers, and no vias outside the fanouts. All 63 repository tests, TypeScript, and git diff --check pass. Browser check: selecting RAM Below loads the PCB, updates the 32 54 mm caption and resource URLs, and opens the Bottom TSX source browser. Regenerated Right, Top, and Left PCB SVGs are byte-for-byte unchanged. Clean Ubuntu CI(https:github.qkg1.toptscircuitquick-configureactionsruns33781557678) passed all four TSX builds, site assembly, 63 tests, and TypeScript. Vercel preview deployment also passed.

🐌 Tiny Contributions (16)

PR #	Impact	Description
#3657	🐌 Tiny	Bumps circuit-to-svg from 0.0.410 to 0.0.412 and refreshes affected schematic SVG snapshots to ensure sheet frames align with their contents.
#3653	🐌 Tiny	Updates the tscircuitcapacity-autorouter dependency from version 0.0.866 to 0.0.874 while maintaining the existing peer dependency contract.
#3544	🐌 Tiny	Summary increase the configured via drill from 0.10 mm to 0.15 mm while retaining the 0.24 mm via pad assert the configured board values and every emitted via dimension update the established progressive and two-bus visual snapshots in place without renaming them This is stacked on 3537, whose branch now includes merged PR 3541. Verification bun test testsreprosrepro-am62l-lpddr4-progressive-fanout.test.tsx --timeout 300000 bun test testsreprosrepro-am62l-lpddr4-two-bus-bga-fanout.test.tsx --timeout 300000 bunx biome check testsfixturescreate-am62l-lpddr4-fanout.tsx testsreprosrepro-am62l-lpddr4-progressive-fanout.test.tsx testsreprosrepro-am62l-lpddr4-two-bus-bga-fanout.test.tsx git diff --check All route geometry and via centers remain unchanged; the SVG visual difference is the larger drill circles. Manufacturing note A 0.15 mm hole inside a 0.24 mm pad leaves a 0.045 mm annular ring per side. The routing and current DRCs pass, but fabrication acceptance remains manufacturer-specific.
#3537	🐌 Tiny	Summary add DDR_DMI0 as the eighth progressive DDR bus, routing AM62L DDR0_DM0 on F2 to LPDDR4 DMI0 on C3 route the singleton bus through inner5 with top-side exits on both component fanouts extend the exact phase, layer, exit, and connectivity assertions update the existing full-board visual snapshot in place without renaming it Dependency Depends on tscircuitfanout-solver112 and its next published release. package.json intentionally remains on tscircuitfanout-solver 0.0.45 until that release exists; this draft was validated against the local solver branch. Validation bun test testsreprosrepro-am62l-lpddr4-progressive-fanout.test.tsx 1 passed, 5,324 assertions bunx tsc --noEmit bunx biome check on changed TypeScript files visually inspected the updated full-board SVG snapshot
#711	🐌 Tiny	Fixes the issue where schematic sheet frames are incorrectly centered at the origin instead of their specified center, ensuring proper rendering of components within the frame.
#864	🐌 Tiny	Replace separate controller and memory previews with a routed two-chip DDR byte-lane example, adding a CircuitPreview showDebugObjects prop and explaining the controller and memory fanout and board-level channel phases.
#862	🐌 Tiny	Add a Routing DDR guide covering bus decomposition, opposing package fanouts, layer allocation, tuning room, and end-to-end verification, along with live CircuitPreview examples for controller and memory byte-lane fanout.
#863	🐌 Tiny	Clarifies the boundaries for DDR fanout by moving synthetic DDR channel endpoints outside each breakout and relying on Cores implicit breakout points.
#2404	🐌 Tiny	Relaxed DRC count overlay The snapshots now show a computed Relaxed DRC errors overlay using the reusable libtestinggetBugReportSnapshotSvg.ts helper. This baseline records Pipeline7: 32 and Pipeline9: 31, using standard benchmark relaxed rules (no board-specific overrides). The helper evaluates existing and new copper together, honors replacement metadata, and renders the same copper. The bug-report creation script now uses it, and the visualization skill documents its usage for future bug reports. Unit tests cover the actual count, input preservation, replaced copper, and explicit rule overrides. The bugreport104 snapshot tests remain test.skip. Merge this baseline before 2389 Capture the complete routed pedometer board on current main (450af9cb90d50880a96f62e9babafc79678031a1) before adopting the fine-pitch pad-escape repair in 2389. This PR changes no solver code or dependencies. Add the pre-route bugreport104 capture and remove its remaining preloaded traces (traces: ). The older public capture is a post-route board with routed-via obstacles, so clearing only its traces is not a valid pre-route input. Point the interactive bugreport104 fixture at that trace-free pre-route capture. Commit separate Pipeline7 and Pipeline9 solved-board SVG snapshots, generated with mains own dependencies and caching disabled. Keep both snapshot tests as test.skip, as requested. They were temporarily enabled locally to generate the snapshots and verify both solvers complete. Render the actual emitted routes, pads, and vias on white; omit connection-debug dots so they do not obscure the BGA escapes. These snapshots record current-main output, not a zero-DRC claim. The exact same input, test files, and SVG paths are used by 2389, which commits the repaired outputs. Merge this PR first so 2389 shows ordinary beforeafter SVG modifications instead of new snapshot files. Manual snapshot regeneration Temporarily change test.skip to test in the two bugreport104-pedometer-pipeline-solved.test.ts files, then run: sh BUN_UPDATE_SNAPSHOTS1 bun test testsbugsbugreport104-pedometer-pipeline7-solved.test.ts testsbugsbugreport104-pedometer-pipeline9-solved.test.ts --timeout 9999999 Restore test.skip before committing or pushing. Both snapshot tests were run locally; TypeScript and the production build were also checked. Main baseline previews Pipeline7 !Pipeline7 current-main solved pedometer board(https:raw.githubusercontent.comtscircuittscircuit-autorouter5f6e4a3dc179461052315a6351b0e414ddc55fe0testsbugs__snapshots__bugreport104-pedometer-pipeline7-solved.snap.svg) Pipeline9 !Pipeline9 current-main solved pedometer board(https:raw.githubusercontent.comtscircuittscircuit-autorouter5f6e4a3dc179461052315a6351b0e414ddc55fe0testsbugs__snapshots__bugreport104-pedometer-pipeline9-solved.snap.svg)
#2392	🐌 Tiny	Adds a fixture for the RP2040 motor controller that creates Pipeline11s simplification solver in the autorouting debugger, validated with existing tests and preserves all traces while reducing vias.
#2387	🐌 Tiny	Summary add a debugger fixture for seveibarpedometer v1.0.6(https:tscircuit.comseveibarpedometer?version1.0.6pcb) preserve the exact partially routed input: 4 layers, 42 mm 26 mm bounds, 304 obstacles, 142 preloaded traces, and 11 remaining connections capture the routing regression around the U2_CHARGER BGA, where preloaded traces run beneath the BGA footprint Current behavior Pipeline7: reaches highDensityRouteSolver but does not complete; the local reproduction was stopped after more than two minutes in that stage Pipeline9: reports solved: true even though Pipeline9HighDensitySolver.stats.nodeCount is 0; its output contains the same 142 preloaded traces and none of the 11 requested connection names Expected behavior Pipeline7 and Pipeline9 should both route the 11 remaining connections while preserving and correctly reasoning about the preloaded traces beneatharound the BGA. Validation bunx tsc --noEmit bun run build reproduced Pipeline7 with bun scriptsrun-sample.ts --pipeline 7 --srj-path downloaded-pedometer-routes.json reproduced Pipeline9 with bun scriptsrun-sample.ts --pipeline 9 --srj-path downloaded-pedometer-routes.json verified the committed SRJ is structurally identical to the downloaded v1.0.6 simpleRouteJson payload This is a fixture-only bug report; it intentionally does not include an autorouter fix.
#2333	🐌 Tiny	Limits the benchmark-all command to only run on dataset01 and dataset18, updates benchmark instructions, and modifies the workflow assertion in the benchmark command test.
#68	🐌 Tiny	Reproduces a visual snapshot of the BGA36 C_BOTTOM pad approach to capture the current bug in the solvers output, without making production changes.
#224	🐌 Tiny	Add MSPM33C321A and MSPM33C3219 exports for the 100-pin PZ LQFP package, add MSPM0C1104 package selection for 20-pin DGS VSSOP and 8-pin DSG WSON parts, and introduce reusable Microcontroller_MSPM0G5117 and Microcontroller_MSPM0G5187 basic-application subcircuits with TI-recommended support.
#140	🐌 Tiny	Add a new benchmarking workflow that runs all available samples, records results, and provides a status update via PR comments.
#15	🐌 Tiny	Renames the RAM placement from Below to Bottom and hides PCB debug overlays in the generated drawings.

GokulPandi-M

PRs #	Impact	Rating	Description
#3667	🐙 Minor	⭐⭐	Fixes overlapping annotations in adjacent LED output branches, improving readability of component references and labels.
#502	🐙 Minor	⭐⭐	Fixes the omission of 3D models in KiCad exports for components that only have OBJ URLs by deriving and embedding corresponding STEP models from EasyEDA.

🐌 Tiny Contributions (4)

PR #	Impact	Description
#538	🐌 Tiny	Fixes the issue where the import of the C2941005 component loses four schematic terminals, ensuring all six terminals are represented in the schematic and PCB.
#240	🐌 Tiny	Reproduces a schematic auto-layout failure where components from adjacent partitions are packed closer than the configured partition gap, causing their rendered annotations to collide.
#497	🐌 Tiny	Adds a characterization reproduction for a bottom-mounted display model in KiCad, isolating the model transform issue without fixing it.
#496	🐌 Tiny	Reproduces the omission of the OBJ-only USB-C model in KiCad export, confirming that the connector body is missing while the footprint remains.

Abse2001

PRs #	Impact	Rating	Description
#229	🐳 Major	⭐⭐⭐	Summary compose the complete Automotive Window Module from the seven reviewed TI subcircuits add a readable multi-sheet TSX example and checked-in schematic snapshot add the Automotive Window Module preset to the system-block builder with semantic power and data connections preserve subcircuits that own internal schematic sheets and generate correctly scoped descendant traces use native default A4 pages for all smaller circuits, including Watchdog and Vref; retain larger sheets only for Main Supply (ANSI B), the MSP430 reference (500 mm 330 mm), and TIDA-01421 Pinch Detection (430 mm 280 mm) verify sheet dimensions and circuit containment in both the standalone example and builder output, without changing component positions or routing verify nine real schematic sheets and KiCad project export TI reference https:www.ti.comsolutionautomotive-window-module?variantid34360subsystemid24690subsystem-reference-design Generated schematic snapshot !Automotive Window Module schematic sheets(https:github.qkg1.toptscircuittiblobfeatautomotive-window-module-completeexamples__snapshots__AutomotiveWindowModule.circuit-schematic.snap.svg?rawtrue) Verification cd system-block-ui bun test 69 passed, 0 failed cd system-block-ui bun run build bun run format:check visually checked all eight circuit sheets after regenerating the snapshots

🐌 Tiny Contributions (2)

PR #	Impact	Description
#535	🐌 Tiny	Documents real L0805 inductor reproductions with provenance and source-identity checks for two EasyEDALCSC component records, ensuring accurate representation in generated schematics and PCBs.
#157	🐌 Tiny	Adds regression tests and fixtures for physical-via export without altering existing implementations or introducing new production code.

imrishabh18

PRs #	Impact	Rating	Description
#2328	🐳 Major	⭐⭐⭐	Fixes trace overlap issue in the force solver related to Bug Report 94, ensuring no overlaps remain in the autorouting process.
#17	🐳 Major	⭐⭐⭐	Visual reproduction !Bug Report 94 before and after force improvement(https:raw.githubusercontent.comtscircuithigh-density-repair01f29ff705b019dc8a18bd2560aa6fe61124b1f543tests__snapshots__bugreport94-force-crossing.snap.svg) Red is source_trace_108, blue is source_trace_138, and green is neighboring source_trace_99. The left panel is the raw force-pass result, where source_trace_108 crosses source_trace_138. The right panel is the final HighDensityForceImproveSolver result: the original crossing is removed without transferring the overlap to source_trace_99. This image is the committed test artifact from tests__snapshots__bugreport94-force-crossing.snap.svg; the test also asserts the corresponding centerline clearances numerically. Summary fix Bug Report 94 in the actual HighDensityForceImproveSolver detect proper segment-interior crossings left by the guarded force rerun recover a small route corridor from the original topology, aligned to the force result project only newly affected neighboring routes and accept a candidate only when protected pairs stay clear and the local violation count decreases add a focused regression for source_trace_108 against both source_trace_138 and source_trace_99 Root cause The force solver enforced point-to-segment clearance without preserving segment-pair topology. Adjacent points could remain individually valid while two segment interiors swapped sides and crossed. The existing guarded rerun removed the original source_trace_108 source_trace_138 crossing, but its whole-node movement transferred the overlap to source_trace_108 source_trace_99. The output therefore looked improved in the snapshot while the final DRC count remained 6. This change adds a post-rerun acceptance step. It reconstructs only the crossing corridor from the original non-crossing topology, aligns it to the fixed force-result segment, resolves any newly touched neighbor locally, and rejects candidates that restore a protected overlap or fail to reduce the number of violating route pairs. Validation bun test 15 passed, 0 failed bun run typecheck passed upstream format, test, and typecheck CI passed full autorouter Bug Report 94 5 DRC errors, no trace-overlap error involving source_trace_108
#234	🐳 Major	⭐⭐⭐	Adds functionality to display recommended TI parts with an expandable MCP JSON response, including caching and error handling for recommendations.
#228	🐳 Major	⭐⭐⭐	Adds a server-only TI Support Intelligence MCP client that fetches and displays TI recommendations in the subcircuit picker, allowing users to see recommended parts alongside local subcircuits.
#225	🐳 Major	⭐⭐⭐	Add a subcircuit picker modal for selecting TI parts within system blocks, allowing users to replace blocks while preserving compatible connections and providing clear notifications for incompatible links.
#11	🐳 Major	⭐⭐⭐	Adds a configurable trace clearance with a default of 0.2 mm, expands foreign-trace visibility barriers, checks clearance-aware connectivity across grid-cell boundaries, and updates snapshots and regression coverage.
#159	🐙 Minor	⭐⭐	Fixes duplicate drill operations in Gerber file exports by deduplicating via drill records based on exact coordinates and drill diameter, ensuring accurate representation of physical vias without unnecessary fallback drills.
#158	🐙 Minor	⭐⭐	Fixes incorrect drill file generation by prioritizing physical layer spans over deprecated routing endpoints during Gerber file export.
#227	🐙 Minor	⭐⭐	Limits the subcircuit picker to show only subcircuits within the selected blocks category, while excluding the current and non-instantiable subcircuits, and preserving alphabetical order within the matching category.

🐌 Tiny Contributions (2)

PR #	Impact	Description
#3666	🐌 Tiny	Updates the implicit copper pour solver dependency to a newer version that accounts for trace clearance and regenerates PCB snapshots for the nRF52810.
#235	🐌 Tiny	Removes the block count, automatic power label, and data-link count from the system-block canvas toolbar, along with adjacent divider and unused calculations and styles, while preserving existing controls.

mohan-bee

PRs #	Impact	Rating	Description
#37	🐳 Major	⭐⭐⭐	Preserves cell boundaries when preferred margins connect all cells, ensuring that section dividers are maintained even when contents are separate.
#1064	🐳 Major	⭐⭐⭐	Fixes trace recovery to prioritize local routes over perimeter detours, improving routing efficiency and accuracy.
#1061	🐳 Major	⭐⭐⭐	motivation same-net ground junction alignment can retain two traces over the same endpoint stub. before img width128 height122 altimage srchttps:github.qkg1.topuser-attachmentsassets145d8d34-aad0-4538-93a1-66cb486acccc the existing esp-12f repro contains duplicate shared-endpoint geometry. after img width112 height72 altimage srchttps:github.qkg1.topuser-attachmentsassetsb4720501-e8fd-44d9-8a26-2c4c7599f94c the solver uses typed ground metadata to preserve one physical pin connection and end the redundant trace at the existing junction. the focused geometry test and affected regression snapshots are updated; no extra before snapshot is added.
#1017	🐳 Major	⭐⭐⭐	Adjusts the placement of downward ground labels to ensure they remain close to their connected pins and directly attached to shared rails, improving schematic clarity and accuracy.
#60	🐳 Major	⭐⭐⭐	Motivation Capture the RV1106G2 camera routing failure with the real board post-processing input. Before A 180-degree differential-pair spine crashed without a full-board regression or snapshot. After Adds the captured board fixture, asserts the current crash, and snapshots the complete board state.
#61	🐳 Major	⭐⭐⭐	Fixes post-processing crash caused by 180-degree spine reversal in differential pair routing.
#262	🐙 Minor	⭐⭐	Add a test and schematic snapshot for a pushbutton whose two schematic contacts connect to the same net, addressing a previously captured failure in Circuit JSON.
#263	🐙 Minor	⭐⭐	Detects two-terminal pushbuttons and switches whose schematic contacts connect to the same net, emitting a fatal configuration error for misconfigured components.
#154	🐙 Minor	⭐⭐	Fixes the issue of zero-length wire-to-via transitions that create unintended Gerber copper, preventing real gesture-controller short reproductions.
#36	🐙 Minor	⭐⭐	Reproduces the issue of missing dividers when section margins are expanded, providing a test case and SVG snapshot for boundary calculations.
#237	🐙 Minor	⭐⭐	Fixes misclassification of two-pin crystals as generic loads, preserving crystal circuit alignment in the layout.
#1045	🐙 Minor	⭐⭐	Merges adjacent same-net branches that share their first segment onto nearby parallel rails, improving schematic alignment.
#1008	🐙 Minor	⭐⭐	Prevents duplicate ground labels on unwired pins of a component to ensure correct schematic representation.

🐌 Tiny Contributions (9)

PR #	Impact	Description
#3663	🐌 Tiny	Updates the tscircuitchecks package from version 0.0.182 to 0.0.183 to enable the released same-net switch contact check in core, allowing board netlist checks to report shorted two-terminal switch contacts.
#2342	🐌 Tiny	Updates the length-matching solver dependency to the latest commit for improved functionality and bug fixes.
#236	🐌 Tiny	Adds a new test and input JSON for reproducing the schematic layout of the board 8822.
#1048	🐌 Tiny	Adds a flag to mark ground nets in various bug report and repro input JSON files to indicate they are ground connections.
#1043	🐌 Tiny	Adds a seven-component input fixture and SVG snapshot test for the isolated power section of board 8090, preserving its routing topology as a regression case.
#1016	🐌 Tiny	This pull request introduces a new JSON file containing the schematic trace for a USB hub sheet. The file includes detailed information about various chips, their dimensions, and pin configurations, which are essential for the schematic representation of the USB hub.
#1002	🐌 Tiny	Adds a focused solver snapshot for the smartwatch power sheet routing case, which was previously unaddressed.
#36	🐌 Tiny	Reproduces a bug where trace-anchored net labels can overlap adjacent net labels without a placement warning.
#51	🐌 Tiny	Updates the circuit-json-to-gerber dependency to version 0.0.101 in the package.json file.

AnasSarkiz

PRs #	Impact	Rating	Description
#3583	🐳 Major	⭐⭐⭐	Fixes duplicated traces in the local autorouter stage output by ensuring that the current solver stage returns the correct trace data without reinserting it as new PCB copper.
#2381	🐳 Major	⭐⭐⭐	Caches exact repeated indexed DRC results during Pipeline 9 joint repair, limits the candidate cache to 64 entries, and exposes cache diagnostics for performance tracking.
#99	🐳 Major	⭐⭐⭐	Summary This consolidates the already reviewed native-size solver work from 95 and 96 into main: add A12, an A03-derived mixed-resolution solver with exact endpoint preservation and a final geometry gate add A11 rip-history costs to break recurring rip-and-reroute cycles expose the solver choices in the package benchmarkdebugger tooling keep A01 and A03 defaults unchanged; the new behavior is opt-in through A11A12 This PR intentionally contains only the shared solver foundation. Compatibility work and the subsequent A11 topology-aware scheduling improvement remain focused dependent PRs. Canonical HD30 baseline Dataset: tscircuitdataset-hd300ad7fe36c3da67469a053cfa98f709f751f844b1 Settings: regular Pipeline 9 nodes, Pipeline 9 copper dimensions, original bounds, shuffle seed 0, effort 1, and a 100,000-iteration cap. Solver Valid native solves --- ---: A01 027 A03 027 A11 727 A12 827 A11 A12 union 1227 All counted solves pass exact route-geometry validation at the original bounds. Validation on ac13ef80da71c3998acb5302329b6b704d0470d1 full package: 82 passed, 2 skipped, 0 failed build passed format check passed canonical four-solver HD30 matrix reproduced.

🐌 Tiny Contributions (1)

PR #	Impact	Description
#2385	🐌 Tiny	Summary add the pedometer Simple Route JSON as bugreport103-pedometer load the large reproduction from publicfixtures in the autorouting debugger Validation verified the JSON parses and has the expected autorouter shape confirmed the committed reproduction matches the supplied board byte-for-byte tests not run, per request (fixture-only change)

ShiboSoftwareDev

PRs #	Impact	Rating	Description
#2361	🐳 Major	⭐⭐⭐	Fixes autorouters relaxed DRC to accept trace endpoints only when they geometrically touch same-net copper on the same PCB layer, preventing false disconnected endpoint errors.
#177	🐳 Major	⭐⭐⭐	Summary read schematic wire geometry from the public kicadts Wire.points API and keep KiCad junctions on renderable traces place ports with the selected symbol unitbody-style transform and emit matching source_port records render embedded KiCad symbol primitives, pin namesnumbers, and visible referencevalue fields instead of generic component boxes preserve standalone text, hierarchical sheets and pins, no-connect markers, rectangles, polylines, and arcs distinguish plain KiCad local labels from shaped global labels, while retaining their unique source_net records preserve hierarchical-sheet pin direction markers, readable text orientation, inset placement, and KiCad sheet colors update the HSP USB LED and pic-programmer native-KiCad-vs-converted snapshots Why The importer previously read a nonexistent wire property, placed pins relative to the page origin, combined pins from every unit, and discarded most embedded symbol and top-level schematic graphics. Real schematics therefore lost wires, used generic boxes, showed misplacedduplicated ports, and omitted labels, annotations, grouping graphics, hierarchical sheets, no-connect markers, and visible junctions. The symbol-local transform now follows KiCads Cartesian symbol coordinates without applying a second Y inversion. Hidden KiCad property text stays hidden, while visible pin and instance text is preserved. Local labels no longer render as boxed global arrows, and 180-degree sheet pins remain readable instead of appearing upside down. This PR is stacked on 176 so its diff contains only the conversion fix and its regression coverage. Visual regression Both real-circuit snapshots keep the native KiCad schematic on the left and the converted Circuit JSON schematic on the right. The regressions verify: HSP USB LED: 13 wire traces, 1 junction, 23 sourceschematic ports, real USBpassivepower symbol geometry, and both source grouping rectangles pic-programmer: 131 wire traces, 26 junctions, 182 sourceschematic ports, 10 plain local-label instances backed by 7 unique source nets, the hierarchical sheet and its 4 readable pin markers, 6 no-connect markers, and 8 dashed source drawing paths Verification bun test testsschematic-source-component-links.test.ts testspic-programmer-parity-sch.test.ts bunx tsc --noEmit bun run format:check bun run build
#105	🐳 Major	⭐⭐⭐	Preserves component ownership for native copper regions, matching solder-mask openings, and retains polygon-cutout provenance for Altium PCB antenna designs.
#3602	🐙 Minor	⭐⭐	Add an end-to-end DDR routing regression test for the AM62L32 and MT53E1G16D1ZW LPDDR4 packages, ensuring proper routing and DRC results.
#3603	🐙 Minor	⭐⭐	Fixes the synchronization of PCB breakout point identity on completed fanout traces before the global routing phase, allowing Pipeline 9 to recognize pre-routed copper as connected to the handoff endpoint and removing unnecessary detours in routing.
#67	🐙 Minor	⭐⭐	Accepts and preserves the show_name and do_not_autoplace children emitted on ordinary schematic properties by KiCad 10, integrating them into Property parsing, construction, accessors, and serialization with round-trip coverage.
#490	🐙 Minor	⭐⭐	Bumps kicad-to-circuit-json to 0.0.122 and implements side-by-side comparisons of native KiCad renders with Circuit JSON round-trip outputs, validating SVG renderability without modifying checked-in source files.
#494	🐙 Minor	⭐⭐	Exports component fabrication-note paths as fp_line graphics on F.Fab or B.Fab, preserving component-relative placement, rotation, and stroke width.
#180	🐙 Minor	⭐⭐	Fixes oversized standalone KiCad board text by using the native font height for rendering, ensuring accurate text size in the conversion to Circuit JSON.
#115	🐙 Minor	⭐⭐	Adds support for binary polygon cutout regions by serializing them with a native region kind and ensuring proper validation and parsing of their properties.
#52	🐙 Minor	⭐⭐	Preserves mechanical and drill-layer PCB text during conversion to Altium format, ensuring that previously lost text elements are retained in the output.
#101	🐙 Minor	⭐⭐	Resolves Altium component parameter expressions to their actual values in the generated Circuit JSON, ensuring that converted schematics display the correct component text instead of formulas.
#103	🐙 Minor	⭐⭐	Adds support for importing and preserving Altium silkscreen graphics, including filled overlay regions with interior holes, and enhances structural coverage for PiDP silkscreen graphics.
#102	🐙 Minor	⭐⭐	Preserves native child-sheet filenames during the source comparison process and ensures they are reused when generating Altium schematic documents, while also deduplicating shared hierarchical documents by case-insensitive filename.
#104	🐙 Minor	⭐⭐	Preserves Altium board cutouts and slot rotation during conversion from Circuit JSON to Altium, ensuring accurate representation of mechanical features.

🐌 Tiny Contributions (4)

PR #	Impact	Description
#491	🐌 Tiny	Preserves imported KiCad component-level symbol artwork instead of overlaying generic chip symbols, maintains native fills, text placement, colors, and standalone schematic graphics, and refreshes all native source-versus-converted schematic snapshots with explicit snapshot-test timeouts.
#495	🐌 Tiny	Fixes the EBAZ4205 schematic rendering issue caused by KiCad 10s upgrade process, ensuring original multi-unit selections are preserved and the correct layout is maintained.
#176	🐌 Tiny	Summary link each imported schematic component to the actual source component ID returned by the database insert keep the inferred component type fully typed without an any cast use the real HSP USB LED KiCad schematic instead of the synthetic one-component fixture show both the HSP USB LED and pic-programmer schematic parity snapshots with native KiCad on the left and imported Circuit JSON on the right Why The importer inserted IDs such as source_component_0 but linked schematic components to fabricated IDs such as Device:R_source. Consumers could not resolve those references. Visual regression The existing repository test now runs against nushackershsp-pcb-introsrcusb_led.kicad_sch. Its snapshot shows the native KiCad source on the left and imported Circuit JSON on the right using an optional horizontal layout in the existing labeled stacking helper. The existing pic-programmer schematic parity test now uses the same side-by-side layout and refreshes its Circuit JSON inspection artifacts. Source revision: ad3fbd582e3915b585c453ea202f591720a1f427 (CERN-OHL-P-2.0), SHA-256 425a817f1c236363eefd6ff8cb23365d2641a43d5f1e057191497046dcf20d75. Verification bun run format:check bunx tsc --noEmit bun test testsschematic-source-component-links.test.ts testspic-programmer-parity-sch.test.ts bun run build
#179	🐌 Tiny	Updates the bundled parser to kicadts 0.0.57 to ensure KiCad 10 schematic properties with show_name and do_not_autoplace parse and round-trip correctly.

techmannih

PRs #	Impact	Rating	Description
#1038	🐳 Major	⭐⭐⭐	Fixes the issue where net label connectors run parallel to host traces by shifting them laterally onto their existing host trace and creating a direct tee instead of a near-parallel connector.

🐌 Tiny Contributions (9)

PR #	Impact	Description
#3584	🐌 Tiny	Reproduces the overlap between the adjacent AUDIO_VRA1, GND, and AUDIO_VRA2 fallback labels in the T113 schematic.
#3585	🐌 Tiny	Add a minimal Trellis Core feedback network with L2, R5, C4, and R7 to reproduce the nearly overlapping BUCK_0V9_FB auto-label trace beside the R5-to-C4 trace and pin the behavior with a schematic snapshot.
#233	🐌 Tiny	Updates the circuit-json-to-altium dependency to a specific commit and refreshes the Bun lockfile for the new Git resolution.
#221	🐌 Tiny	Summary replace explicit netlabel elements with named native traces remove legacy manual label positioning helpers and update connectivity assertions refresh only existing affected snapshots and add a guard against reintroducing manual netlabels Validation bun run typecheck focused tests: 20 pass full bun test: 121 pass, 1 pre-existing failure in PowerSupply_WindowModule.test.tsx for missing sheet dimensions existing snapshots updated: 42 modified, 0 added Biome formatting passes for all PR sourcetest files; repository-wide check is blocked only by unrelated untracked files under tmp
#226	🐌 Tiny	Fixes the length of the port stems for the LM5050 TVS symbol to align with the symbol body.
#223	🐌 Tiny	Fixes Altium exporter to use five-digit schematic fractional coordinates and prevents rendering issues with giant symbol lines and filled polygons in Real View.
#222	🐌 Tiny	Updates the circuit-json-to-altium dependency to a specific commit and refreshes the Bun lockfile for the new Git resolution.
#92	🐌 Tiny	Fixes the handling of filled rectangle colors in Altium exports by using the rectangles color as a fallback when fill_color is omitted and preserving fill_color when provided, affecting both component symbols and sheet annotations.
#93	🐌 Tiny	Fixes the handling of fractional coordinates in Altium schematics by ensuring they use a five-digit fixed-point representation, preventing rendering issues in native Altium viewers.

0hmX

PRs #	Impact	Rating	Description
#1	🐳 Major	⭐⭐⭐	Summary expand the generator from Dataset 01 to 15 pinned SRJ source families add dataset selection, bounded workers, per-problem timeouts, and serialized crash-safe writes regenerate the corpus with 296 valid records from 14 represented families add per-source provenancecounts and a manifest writer document generation and add source inventory coverage SRJ13 is supported by the generator but has no committed records because its inputs fail before reaching trace simplification in the winding-breakout stage. Corpus 296 records 7,178 inputoutput traces 390,651 input route points 74,838 output route points SHA-256: b7ee77cc018862647e44ee9e160bf2558caef99781c5ec80f5c0e2d57b8ebb99 Validation bun run check 296 Pipeline 11 replay validations 2 tests, 598 assertions

🐌 Tiny Contributions (2)

PR #	Impact	Description
#2326	🐌 Tiny	Adds a reproduction of the QFP16 Pipeline 9 with extra vias, documenting a routing-quality regression without changing solver behavior.
#154	🐌 Tiny	Summary add the exact northeast SoC and DRAM breakout SRJs under testsfixturessoc-dramnortheast add a selectable Cosmos debugger page using GenericSolverDebugger and FanoutSolver add a focused characterization test and SVG snapshots for both fixtures Current solver behavior This PR intentionally does not change solver logic. Both fixtures exhaust 256 layer assignments and fail with FanoutSolver: best layer assignment routed 033 connections. The current inferred directions are up for the SoC and down for the DRAM. Verification bun test testssoc-dram-northeast-failure.test.ts bun run typecheck

KrishnaX12

🐌 Tiny Contributions (6)

PR #	Impact	Description
#190	🐌 Tiny	Description Downloading the 3D PNG for seveibarusb-c-flashlight places the USB-C connector away from its solder pads. The same connector is positioned correctly in the interactive viewer on docs.tscircuit.com. This PR adds a reproduction test using the Circuit JSON from the published v1.0.0 release and a full-board snapshot that captures the incorrect placement on the current main branch. The exposed pad row behind the connector makes the offset easy to see. No renderer code is changed. The snapshot records the current incorrect output, so the test passes while preserving the bug for the related fix. Fixture Package: seveibarusb-c-flashlight Version: v1.0.0 Release ID: 35fa29c2-6067-4d62-9c97-4b418fb4870f Circuit JSON: distindexcircuit.json 3D model: URL referenced by the published release Reproduction bun test testsreprousb-c-flashlight-origin.test.ts Current 3D PNG output !USB-C connector incorrectly offset in downloaded 3D PNG(https:github.qkg1.topuser-attachmentsassetsaaa3f718-79c4-4d41-be7a-4cd78d24215d) In https:docs.tscircuit.com !USB-C connector correctly positioned in the interactive viewer(https:github.qkg1.topuser-attachmentsassets30918d71-4234-490d-9625-99c36263f473) Validation Reproduction test passes Formatting passes TypeScript passes Snapshot visually inspected fix: 189
#131	🐌 Tiny	Fixes the SVG renderer to correctly display active component display modes for polarized capacitors in schematics.
#119	🐌 Tiny	Fixes schematic bus rendering using the actual Altium record model by parsing and rendering Bus and BusEntry records accurately.
#99	🐌 Tiny	Fixes rendering order of opaque component graphics to ensure pin labels are not obscured by filled component bodies.
#98	🐌 Tiny	Fixes rendering of active-low overbars in schematic SVG text by parsing Altium negation markers and rendering them correctly in SVG format.
#100	🐌 Tiny	Pins the altiumts component to the merged v0.0.41 main commit and refreshes schematic SVG snapshots affected by the corrected component body and pin-label paint order.

Sang-it

PRs #	Impact	Rating	Description
#103	🐙 Minor	⭐⭐	Adds a uniform solderpaste layer by reducing pad dimensions and applying lens distortion for non-circular top pads in LightBurn exports.

🐌 Tiny Contributions (3)

PR #	Impact	Description
#108	🐌 Tiny	Add STM32 and RP2040 photodiode examples for BiscuitBoard V2, including routing through prefabricated vias and adding PCB snapshots and tests.
#106	🐌 Tiny	Add the independent 75 x 55 mm BiscuitBoard V2 clad with 2.5 mm-pitch corner and center via fields, and copy the STM32TMC5130 controller onto V2 with placements defined directly in the controller TSX and prefabricated-via routing.
#110	🐌 Tiny	Restores the includeBoardFiles configuration removed by a previous PR, retaining all 20 previously included example board entries.

anil08607

🐌 Tiny Contributions (3)

PR #	Impact	Description
#45	🐌 Tiny	Fixes the inability to scroll vertically on the left control panel when content exceeds the viewport height on smaller screens.
#115	🐌 Tiny	Adds support for newer Altium RECORD209 note objects that were previously dropped during schematic round trips, converting these notes into schematic text and filled rectangle annotations, preserving the original note content and appearance instead of silently losing them.
#119	🐌 Tiny	Updates the altiumts dependency to a newer commit version in package.json

Repository Owners

Repository	Codeowners
builder	seveibar
pcb-viewer	seveibar, ShiboSoftwareDev, Abse2001
footprints-old	seveibar
footprinter	seveibar, techmannih
3d-viewer	ShiboSoftwareDev, Abse2001
winterspec	seveibar, ShiboSoftwareDev
jscad-electronics	seveibar, techmannih, ShiboSoftwareDev, anas-sarkez
circuit-to-svg	imrishabh18
schematic-symbols	seveibar, imrishabh18, techmannih
circuit-json-to-gerber	seveibar, ShiboSoftwareDev
tscircuit.com	seveibar, imrishabh18
issue-roulette	Anshgrover23
schematic-corpus	Abse2001
copper-pour-solver	seveibar, ShiboSoftwareDev
common	seveibar, Abse2001
circuit-to-canvas	ShiboSoftwareDev, Abse2001, techmannih
circuit-json-to-lbrn	AnasSarkiz
pcbburn.com	AnasSarkiz
high-density-repair03	Abse2001
fabrication-operator-ui	AnasSarkiz
layerweaver	0hmx

Repositories by Owner

User	Repo
seveibar	builder
	pcb-viewer
	footprints-old
	footprinter
	winterspec
	jscad-electronics
	schematic-symbols
	circuit-json-to-gerber
	tscircuit.com
	copper-pour-solver
	common
ShiboSoftwareDev	pcb-viewer
	3d-viewer
	winterspec
	jscad-electronics
	circuit-json-to-gerber
	copper-pour-solver
	circuit-to-canvas
Abse2001	pcb-viewer
	3d-viewer
	schematic-corpus
	common
	circuit-to-canvas
	high-density-repair03
techmannih	footprinter
	jscad-electronics
	schematic-symbols
	circuit-to-canvas
anas-sarkez	jscad-electronics
imrishabh18	circuit-to-svg
	schematic-symbols
	tscircuit.com
Anshgrover23	issue-roulette
AnasSarkiz	circuit-json-to-lbrn
	pcbburn.com
	fabrication-operator-ui
0hmx	layerweaver

Development

Prerequisites

• Bun runtime
• .env file with required API keys:

  GITHUB_TOKEN=your_github_token
  OPENAI_API_KEY=your_openai_api_key
  DISCORD_TOKEN=your_discord_token (optional, for Discord integration)
  SLACK_BOT_TOKEN=your_slack_token (optional, for Slack integration)
  

Available Scripts

Core Generation Scripts

• bun run generate:weekly - Generate current week's contribution overview
• bun run generate:monthly - Generate current month's contribution overview
• bun run generate:changelog - Generate monthly changelog from PRs

Analysis & Testing

• bun run analyze-pr - Analyze a single PR (interactive prompt)
• bun run test:github - Test GitHub API integration

Notifications & Sync

• bun run notifications:issues - Send notifications for new issues
• bun run notifications:pr - Send notifications for new PRs
• bun run sync:discord - Sync contributor roles with Discord

Data Export

• bun run export:sponsorship - Generate sponsorship data CSV

Development

• bun run dev - Start development server for web UI
• bun run build - Build for production
• bun run format - Format code with Biome

Usage Examples

# Generate this week's contribution overview
bun run generate:weekly

# Generate current month's overview
bun run generate:monthly

# Analyze a specific PR
bun run analyze-pr

# Test your GitHub token setup
bun run test:github