Group and row-pack decoupling caps to eliminate chip overlaps (fixes #15)#68
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Pearltechie wants to merge 2 commits intotscircuit:mainfrom
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Group and row-pack decoupling caps to eliminate chip overlaps (fixes #15)#68Pearltechie wants to merge 2 commits intotscircuit:mainfrom
Pearltechie wants to merge 2 commits intotscircuit:mainfrom
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Fixes tscircuit#15. The RP2040 example produced four chip overlaps because the layout pipeline treated decoupling capacitors like ordinary 2-pin chips. Three coordinated fixes give each main chip's bypass network a tidy, deterministic row. 1. Converter (getInputProblemFromCircuitJsonSchematic) - Tag 2-pin passives (resistors, capacitors, diodes, ferrites, inductors) with availableRotations: [0, 180] so downstream solvers can recognise them as orientation-restricted. - Detect ground / positive-supply rails by net name (GND/VSS/VEE, VCC/VDD/VBUS/V3_3 family, etc.) and set isGround / isPositiveVoltageSource on the matching nets. 2. Decoupling-cap identification - Walk one hop across pinStrongConnMap in getNetIdsForPin so a cap whose hot pin tees directly off a chip pin still resolves to the supply net that chip pin sits on (the common RP2040 wiring style). - Add a net-pair fallback in findMainChipIdForCap: when a cap has no direct strong neighbour, the main chip is the chip with the most pins on the cap's net pair. This catches caps wired purely through the power and ground rails. 3. Inner-partition packing - Decoupling-cap partitions now bypass PackSolver2 and use a deterministic centred row layout sorted by chipId, with spacing controlled by decouplingCapsGap (falling back to chipGap). Test results RP2040Circuit complete pipeline execution PASS (overlaps: 0) RP2040Circuit InputProblem conversion PASS The getInputProblemFromCircuitJsonSchematic01 inline snapshot was updated to reflect the new metadata (availableRotations on 2-pin passives, isGround and isPositiveVoltageSource on supply nets).
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The IdentifyDecouplingCapsSolver06 test imported `problem` from `LayoutPipelineSolver06.page.tsx`, which transitively pulled in `@tscircuit/schematic-viewer` -> `circuit-to-svg`. The latter no longer exports `convertCircuitJsonToSchematicSimulationSvg`, so the test crashed with "SyntaxError: Export named ... not found". Splitting the problem definition into a sibling `.problem.ts` (no React, no visualization deps) gives the test a clean import path and removes the crash. The page re-exports `problem` for backwards compatibility. Result: 18 pass, 1 skip, 0 fail.
Author
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Hey @seveibar 👋 just wanted to check in on this — all the CI checks (tests, type-check, formatting) are passing and I've included a demo video in the description. Let me know if there's anything you'd like me to change or if you have any questions about the approach! |
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Fixes #15.
Problem
The RP2040 example (
tests/LayoutPipelineSolver/RP2040Circuit.test.ts) produced 4 chip overlaps in the final layout because decoupling capacitors were treated like ordinary 2-pin chips:IdentifyDecouplingCapsSolverandSingleInnerPartitionPackingSolverwere already partly in place, but identified 0 decap groups on RP2040 because:availableRotationson 2-pin passives.isGround/isPositiveVoltageSourceon supply nets.getNetIdsForPinonly looked at direct pin↔net connections, missing caps that tee off another chip's pin via a strong pin↔pin connection (the common RP2040 wiring style).Fix
Three coordinated changes:
1. Converter (
lib/testing/getInputProblemFromCircuitJsonSchematic.ts)availableRotations: [0, 180].GND/VSS/VEE→isGround: true;VCC/VDD/VBUS/V3_3/V5/...→isPositiveVoltageSource: true.2. Decoupling-cap identification (
lib/solvers/IdentifyDecouplingCapsSolver/IdentifyDecouplingCapsSolver.ts)getNetIdsForPinnow walks one hop acrosspinStrongConnMapso a cap pin that's strong-connected to a chip pin still resolves to whatever supply net the chip pin sits on.findMainChipIdForCapfalls back to a net-pair search when there's no direct strong neighbour: the main chip becomes the chip with the most pins on the cap's normalised(GND, V*)net pair.3. Inner-partition packing (
lib/solvers/PackInnerPartitionsSolver/SingleInnerPartitionPackingSolver.ts)Decoupling-cap partitions bypass
PackSolver2and use a deterministic centred row layout sorted bychipId, with spacing controlled bydecouplingCapsGap(falling back tochipGap).Verification
Both
RP2040Circuit complete pipeline execution(assertsoverlaps.length === 0) andRP2040Circuit InputProblem conversionpass. The full suite is 17 pass / 1 skip, with one pre-existing unrelated failure inIdentifyDecouplingCapsSolver06.test.ts(circuit-to-svgno longer exportsconvertCircuitJsonToSchematicSimulationSvg) that is unaffected by this PR.The
getInputProblemFromCircuitJsonSchematic01inline snapshot was updated to reflect the newavailableRotations/isGround/isPositiveVoltageSourcefields.Demo Video
rec-324c1315-3004-494c-abca-dfe3ec7cfe41-subtitled.mp4
/claim #15