feat: add PowerNetVerticalBiasSolver to improve schematic layout#71
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selenaalpha77-sketch wants to merge 3 commits intotscircuit:mainfrom
Open
feat: add PowerNetVerticalBiasSolver to improve schematic layout#71selenaalpha77-sketch wants to merge 3 commits intotscircuit:mainfrom
selenaalpha77-sketch wants to merge 3 commits intotscircuit:mainfrom
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…ircuit#12) Adds a new post-pack pipeline phase (PowerNetVerticalBiasSolver) that improves schematic layout readability by applying a vertical bias based on power/ground net connectivity: - Chips connected to positive-voltage nets (VCC, VDD, V+) are shifted upward, following conventional schematic layout where power is at the top. - Chips connected to ground nets (GND, VSS) are shifted downward. - Chips with no power/ground affiliation or balanced connections remain at their packed positions. The solver runs as the final phase in LayoutPipelineSolver after PartitionPackingSolver. getOutputLayout() and visualize() both return the biased layout when available. Fixes tscircuit#12
…sing export convertCircuitJsonToSchematicSimulationSvg was not exported in the old version of circuit-to-svg, causing test failures. Update to latest compatible versions.
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Fixes #12
/claim #12
Adds
PowerNetVerticalBiasSolveras a post-packing phase inLayoutPipelineSolver:This follows the conventional schematic layout principle where power flows downward, making schematics more readable and matching industry standards.
Changes
lib/solvers/PowerNetVerticalBiasSolver/PowerNetVerticalBiasSolver.ts— new solverlib/solvers/LayoutPipelineSolver/LayoutPipelineSolver.ts— integrates new solvertests/LayoutPipelineSolver/PowerNetVerticalBias.test.ts— test coveragepackage.json— update deps to fix test suite (circuit-to-svg missing export)