Roadmap

Jump to bottom Edit New page

cdeschryver edited this page Oct 28, 2014 · 3 revisions

The following feature are planned to be included in future releases:

port to the Xilinx Zynq architecture and the ZedBoard (underway)
port tool flow to Vivado (underway)

Someday / Maybe:

simulation of the hardware-software communication with an RTL simulator
- no board needed
- test and debug your design and interaction with the host software before time consuming synthesis