fix smem path in lsu and diplomacy, fix mmio base addr

Author: richardyrh

src/main/scala/radiance/cluster/RadianceSharedMemComponents.scala

@@ -6,6 +6,7 @@ import freechips.rocketchip.diplomacy.{AddressSet, BufferParams}
 import freechips.rocketchip.tilelink._
 import gemmini._
 import org.chipsalliance.cde.config.Parameters
+import org.chipsalliance.diplomacy.DisableMonitors
 import org.chipsalliance.diplomacy.lazymodule._
 import radiance.memory._
 import radiance.subsystem._
@@ -56,7 +57,9 @@ class RadianceSharedMemComponents(
     tile.smemNodes.zipWithIndex.map { case (m, lid) =>
       val smemFanoutXbar = LazyModule(new TLXbar())
       smemFanoutXbar.suggestName(f"rad_smem_fanout_cl${clusterParams.clusterId}_c${cid}_l${lid}_xbar")
-      smemFanoutXbar.node :=* AddressOrNode(clusterParams.baseAddr) :=* m
+      smemFanoutXbar.node :=* DisableMonitors { implicit p =>
+        AddressOrNode(clusterParams.baseAddr) :=* m
+      }
       smemFanoutXbar.node
     }.toList
   }.toList

src/main/scala/radiance/muon/LSU.scala

@@ -1282,8 +1282,8 @@ class LoadStoreUnit(implicit p: Parameters) extends CoreModule()(p) {
         io.shmemReq.valid := false.B
         reqGen.io.memRequest.ready := io.globalMemReq.ready
     }.otherwise {
-        io.globalMemReq.valid := reqGen.io.memRequest.valid
-        io.shmemReq.valid := true.B
+        io.globalMemReq.valid := false.B
+        io.shmemReq.valid := reqGen.io.memRequest.valid
         reqGen.io.memRequest.ready := io.shmemReq.ready
     }
 

src/main/scala/radiance/muon/MuonTile.scala

@@ -10,6 +10,7 @@ import freechips.rocketchip.subsystem._
 import freechips.rocketchip.tile._
 import freechips.rocketchip.tilelink._
 import org.chipsalliance.cde.config._
+import org.chipsalliance.diplomacy.DisableMonitors
 import org.chipsalliance.diplomacy.lazymodule.LazyModule
 import radiance.cluster.SoftResetFinishNode
 import radiance.memory._
@@ -148,7 +149,9 @@ class MuonTile(
   }
 
   val smemNodes = innerSmemNodes.map(node => {
-    TLBuffer() := node
+    DisableMonitors { implicit p =>
+      TLBuffer() := node
+    }
   })
 
   val icacheWordNode = muonParams.icache match {
@@ -212,6 +215,7 @@ class MuonTile(
 
   val (l0dOut, l0dIn, flushRegNode) = muonParams.dcache.map { l0dParams =>
     require(muonParams.dcache.map(_.blockBytes).getOrElse(coalescedReqWidth) == coalescedReqWidth)
+    println(f"l0d flush address is ${muonParams.peripheralAddr}%x")
     val l0d = LazyModule(new TLULNBDCache(TLNBDCacheParams(
       id = tileId,
       cache = l0dParams,

src/main/scala/radiance/subsystem/Configs.scala

@@ -100,15 +100,14 @@ class WithMuonCores(
         icacheUsingD = l0i,
         dcache = l0d,
         l1CacheLineBytes = clusterParams.l1Config.blockBytes,
-        peripheralAddr = clusterParams.baseAddr + clusterParams.peripheralAddrOffset +
-          0x200 + 0x100 * coreIdOffset,
+        peripheralAddr = clusterParams.baseAddr + clusterParams.peripheralAddrOffset
       )
       List.tabulate(n)(i => MuonTileAttachParams(
         muon.copy(
           tileId = i + idOffset,
-          coreId = i + coreIdOffset,
+          coreId = i /* + coreIdOffset */,
           clusterId = clusterParams.clusterId,
-          peripheralAddr = muon.peripheralAddr + i * 0x100,
+          peripheralAddr = muon.peripheralAddr + 0x200 + i * 0x100,
         ),
         crossing
       )) ++ prev