make dirty lines also update metadata, fix tlc to tlul logic

Author: richardyrh

src/main/scala/radiance/memory/MuonDCache.scala

@@ -83,6 +83,7 @@ class CacheFlushUnit(implicit edge: TLEdgeOut, p: Parameters) extends L1HellaCac
     val wrap = flushCounter.inc()
     when (wrap) {
       flushing := false.B
+      printf("CACHE FLUSH COMPLETE!\n")
     }
   }
 
@@ -114,22 +115,25 @@ class CacheFlushUnit(implicit edge: TLEdgeOut, p: Parameters) extends L1HellaCac
   val (isDirty, respType, nextCoh) = meta.coh.onCacheControl(M_FLUSH)
   // invalid line gets automatically skipped
 
-  // clean line: invalidate in tag array only
-  io.meta_write.valid := metaValid && meta.coh.isValid() && !isDirty
+  // valid line: invalidate in tag array
+  // need double fire for dirty lines
+  io.meta_write.valid := metaValid && meta.coh.isValid() && (!isDirty || io.wb_req.ready)
   io.meta_write.bits.way_en := metaReq.way_en
   io.meta_write.bits.idx := metaReq.idx
   io.meta_write.bits.tag := meta.tag
   io.meta_write.bits.data.tag := meta.tag
   io.meta_write.bits.data.coh := nextCoh
 
   // dirty line: send a writeback request with voluntary release
-  io.wb_req.valid := metaValid && meta.coh.isValid() && isDirty
+  io.wb_req.valid := metaValid && meta.coh.isValid() && isDirty && io.meta_write.ready
   io.wb_req.bits.idx := metaReq.idx
   io.wb_req.bits.tag := meta.tag
   io.wb_req.bits.source := 0.U // TODO: does this work??
   io.wb_req.bits.param := respType
   io.wb_req.bits.way_en := metaReq.way_en
   io.wb_req.bits.voluntary := true.B
+
+  assert(!io.wb_req.fire || io.meta_write.fire)
 }
 
 class MuonNonBlockingDCache(staticIdForMetadataUseOnly: Int,

src/main/scala/radiance/memory/TLNBDCache.scala

@@ -226,7 +226,8 @@ class TLNBDCacheModule(outer: TLNBDCache)(implicit p: Parameters) extends LazyMo
         when (valid) {
           fio.start := true.B
         }
-        !fio.busy
+        true.B
+        // !fio.busy
       })),
     )
   }

src/main/scala/radiance/memory/TLULNBDCache.scala

@@ -35,14 +35,57 @@ class TLCToTLULNode(beatBytes: Int)(implicit p: Parameters) extends LazyModule {
     }
   )
   lazy val module = new LazyModuleImp(this) {
-    (node.in.map(_._1) zip node.out.map(_._1)).foreach { case (i, o) =>
+    (node.in.map(_._1) zip node.out).foreach { case (tlIn, (tlOut, oe)) =>
       // out (ul) has no E bundle, but in (c) does
-      o.a <> i.a
-      i.b <> o.b
-      o.c <> i.c
-      i.d <> o.d
 
-      i.e.ready := true.B
+      tlOut.a.valid := tlIn.a.valid || tlIn.c.valid
+      tlIn.a.ready := tlOut.a.ready && (!tlIn.c.valid) // C channel has priority over A
+      tlOut.a.bits := tlIn.a.bits
+      when (tlIn.c.valid) {
+        tlOut.a.bits := oe.Put(tlIn.c.bits.source, tlIn.c.bits.address, tlIn.c.bits.size, tlIn.c.bits.data)._2
+        tlOut.a.bits.source := tlIn.c.bits.source
+        // tlOut.a.bits.data := tlIn.c.bits.data
+        // tlOut.a.bits.size := tlIn.c.bits.size
+      }
+      // C channel ReleaseData translates to PutFull, A channel AcquireBlock translates to Get
+      tlOut.a.bits.opcode := Mux(tlIn.c.valid, TLMessages.PutFullData, TLMessages.Get)
+      // squash A channel param to 0 (normally represents permission change, we don't want this)
+      tlOut.a.bits.param := 0.U
+
+      assert(!tlIn.a.valid || (tlIn.a.bits.opcode === TLMessages.AcquireBlock))
+      assert(!tlIn.c.valid || (tlIn.c.bits.opcode === TLMessages.ReleaseData))
+
+      assert(!tlOut.b.valid, "no probes allowed")
+
+      tlOut.c.valid := false.B
+      tlOut.c.bits := DontCare
+      tlIn.c.ready := tlOut.a.ready // priority over A
+
+      tlIn.d.valid := tlOut.d.valid
+      tlIn.d.bits := tlOut.d.bits
+      tlIn.d.bits.opcode := Mux(tlOut.d.bits.opcode === TLMessages.AccessAckData,
+        TLMessages.GrantData, // response for A channel AcquireBlock
+        TLMessages.ReleaseAck // response for C channel ReleaseData
+      )
+      tlIn.d.bits.sink := Counter(
+        tlIn.d.fire && tlIn.d.bits.opcode === TLMessages.GrantData,
+        1 << tlIn.params.sinkBits)._1
+      tlOut.d.ready := tlIn.d.ready
+
+      tlOut.e.valid := false.B
+      tlOut.e.bits := DontCare
+      tlIn.e.ready := true.B // silently sink GrantAck's
+
+      dontTouch(tlIn.a)
+      dontTouch(tlIn.b)
+      dontTouch(tlIn.c)
+      dontTouch(tlIn.d)
+      dontTouch(tlIn.e)
+      dontTouch(tlOut.a)
+      dontTouch(tlOut.b)
+      dontTouch(tlOut.c)
+      dontTouch(tlOut.d)
+      dontTouch(tlOut.e)
     }
   }
 }
@@ -69,56 +112,7 @@ class TLULNBDCacheModule(outer: TLULNBDCache) extends LazyModuleImp(outer)
 
   require(outer.outNode.in.length == 1, s"tlcOutNode has ${outer.outNode.in.length} inputs")
 
-  val (tlIn, _) = outer.outNode.in.head
-  val (tlOut, oe) = outer.outNode.out.head
-
-  tlOut.a.valid := tlIn.a.valid || tlIn.c.valid
-  tlIn.a.ready := tlOut.a.ready && (!tlIn.c.valid) // C channel has priority over A
-  tlOut.a.bits := tlIn.a.bits
-  when (tlIn.c.valid) {
-    tlOut.a.bits := oe.Put(tlIn.c.bits.source, tlIn.c.bits.address, tlIn.c.bits.size, tlIn.c.bits.data)._2
-    tlOut.a.bits.source := tlIn.c.bits.source
-    // tlOut.a.bits.data := tlIn.c.bits.data
-    // tlOut.a.bits.size := tlIn.c.bits.size
-  }
-  // C channel ReleaseData translates to PutFull, A channel AcquireBlock translates to Get
-  tlOut.a.bits.opcode := Mux(tlIn.c.valid, TLMessages.PutFullData, TLMessages.Get)
-  // squash A channel param to 0 (normally represents permission change, we don't want this)
-  tlOut.a.bits.param := 0.U
-
-  assert(!tlIn.a.valid || (tlIn.a.bits.opcode === TLMessages.AcquireBlock))
-  assert(!tlIn.c.valid || (tlIn.c.bits.opcode === TLMessages.ReleaseData))
-
-  assert(!tlOut.b.valid, "no probes allowed")
-
-  tlOut.c.valid := false.B
-  tlOut.c.bits := DontCare
-  tlIn.c.ready := tlOut.a.ready // priority over A
-
-  tlIn.d.valid := tlOut.d.valid
-  tlIn.d.bits := tlOut.d.bits
-  tlIn.d.bits.opcode := Mux(tlOut.d.bits.opcode === TLMessages.AccessAckData,
-    TLMessages.GrantData, // response for A channel AcquireBlock
-    TLMessages.ReleaseAck // response for C channel ReleaseData
-  )
-  tlIn.d.bits.sink := Counter(
-    tlIn.d.fire && tlIn.d.bits.opcode === TLMessages.GrantData,
-    1 << tlIn.params.sinkBits)._1
-  tlOut.d.ready := tlIn.d.ready
-
-  tlOut.e.valid := false.B
-  tlOut.e.bits := DontCare
-  tlIn.e.ready := true.B // silently sink GrantAck's
-
-  dontTouch(tlIn.a)
-  dontTouch(tlIn.b)
-  dontTouch(tlIn.c)
-  dontTouch(tlIn.d)
-  dontTouch(tlIn.e)
-  dontTouch(tlOut.a)
-  dontTouch(tlOut.b)
-  dontTouch(tlOut.c)
-  dontTouch(tlOut.d)
-  dontTouch(tlOut.e)
+  // val (tlIn, _) = outer.outNode.in.head
+  // val (tlOut, oe) = outer.outNode.out.head
 }