@@ -762,26 +762,36 @@ class LsuResponse(implicit p: Parameters) extends CoreBundle {
762762 val debugId : Option [UInt ] = lsuDerived.debugIdBits.map { bits => UInt (bits.W ) }
763763}
764764
765- /*
766- # Downstream memory interface
767-
768- The LSU Memory Request interface is per-warp with separate data / address / tmask per lane,
769- but the tag is shared across all lanes.
770-
771- The core's memory interface is fully per-LSU-lane, with a per-LSU-lane tag as well. Generally, for coalesced requests,
772- the responses will come back together, but for uncoalesced requests, no such guarantee is made. As such, we
773- need to support partial writes into the load data staging SRAM, and we need to keep track of which words in a row
774- are valid, only advancing the state machine to begin writing back once all of them are.
775-
776- As such, we need to convert from LSU memory request to core memory request, and the LSU Memory Response interface
777- should support per-LSU-lane valids. We don't need to have a separate tag for each core memory request lane, since
778- the coalescer treats each lane as a separate client with a separate source id space.
779- We also need to convert from core memory response to LSU memory response(s). This is done very naively,
780- by picking the first valid lane on the core side, and filtering only those responses whose tag matches it.
781-
782- In the future, it may be possible to begin writing back to register files once a packet is ready (or even
783- individual lanes within a packet), rather than the full warp
784- */
765+ // ---------------------------
766+ // Downstream memory interface
767+ // ---------------------------
768+ //
769+ // The LSU Memory Request has a full-warp-wide interface, with a single tag
770+ // shared across all lanes, and with per-lane data / address / tmask.
771+ //
772+ // On the other hand, the core's memory interface is fully per-LSU-lane, with a
773+ // per-LSU-lane tag as well. Generally, for coalesced requests, the responses
774+ // will come back together, but for uncoalesced requests, no such guarantee is
775+ // made.
776+ //
777+ // Because the LSU always expects responses for all per-lane reqs to come back
778+ // at the same time "atomically" as a result of its warp-wide interface, we
779+ // need to support partial writes into the load data staging SRAM, and keep
780+ // track of which words in a row are valid, only advancing the state machine to
781+ // begin writing back once all of them are.
782+ //
783+ // As such, we need to convert from LSU request to core request, and the LSU
784+ // response should be converted from per-LSU-lane core responses. We don't need
785+ // to have a separate tag for each core memory request lane, since the
786+ // coalescer treats each lane as a separate client with a separate source id
787+ // space. Converting from core memory response to LSU memory response(s) is
788+ // done very naively, by picking the first valid lane on the core side, and
789+ // filtering only those responses whose tag matches it.
790+ //
791+ // In the future, it may be possible to begin writing back to register files
792+ // once a packet is ready (or even individual lanes within a packet), rather
793+ // than the full warp.
794+
785795class LsuMemTag (implicit p : Parameters ) extends CoreBundle {
786796 val token = new LsuQueueToken
787797 val packet = UInt (lsuDerived.packetBits.W )
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