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Add cyclotron-as-a-tile blackbox and DPI shim
WIP; missing IO for smem/flush/barriers/softreset.
1 parent 09a8040 commit b161dd2

6 files changed

Lines changed: 368 additions & 3 deletions

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‎cyclotron‎

Submodule cyclotron updated 108 files

‎src/main/resources/csrc/Cyclotron.cc‎

Lines changed: 49 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -171,6 +171,55 @@ void cyclotron_frontend(
171171
);
172172
}
173173

174+
void cyclotron_tile_tick_rs();
175+
176+
void cyclotron_tile_tick(
177+
uint8_t* imem_req_valid_ptr,
178+
uint8_t imem_req_ready,
179+
uint32_t* imem_req_bits_address_ptr,
180+
uint64_t* imem_req_bits_tag_ptr,
181+
uint8_t* imem_resp_ready_ptr,
182+
uint8_t imem_resp_valid,
183+
uint64_t imem_resp_bits_tag,
184+
uint64_t imem_resp_bits_data,
185+
uint8_t* dmem_req_valid_vec,
186+
const uint8_t* dmem_req_ready_vec,
187+
uint8_t* dmem_req_bits_store_vec,
188+
uint32_t* dmem_req_bits_address_vec,
189+
uint8_t* dmem_req_bits_size_vec,
190+
uint32_t* dmem_req_bits_tag_vec,
191+
uint32_t* dmem_req_bits_data_vec,
192+
uint8_t* dmem_req_bits_mask_vec,
193+
uint8_t* dmem_resp_ready_vec,
194+
const uint8_t* dmem_resp_valid_vec,
195+
const uint32_t* dmem_resp_bits_tag_vec,
196+
const uint32_t* dmem_resp_bits_data_vec,
197+
uint8_t* finished_ptr
198+
) {
199+
(void)imem_req_valid_ptr;
200+
(void)imem_req_ready;
201+
(void)imem_req_bits_address_ptr;
202+
(void)imem_req_bits_tag_ptr;
203+
(void)imem_resp_ready_ptr;
204+
(void)imem_resp_valid;
205+
(void)imem_resp_bits_tag;
206+
(void)imem_resp_bits_data;
207+
(void)dmem_req_valid_vec;
208+
(void)dmem_req_ready_vec;
209+
(void)dmem_req_bits_store_vec;
210+
(void)dmem_req_bits_address_vec;
211+
(void)dmem_req_bits_size_vec;
212+
(void)dmem_req_bits_tag_vec;
213+
(void)dmem_req_bits_data_vec;
214+
(void)dmem_req_bits_mask_vec;
215+
(void)dmem_resp_ready_vec;
216+
(void)dmem_resp_valid_vec;
217+
(void)dmem_resp_bits_tag_vec;
218+
(void)dmem_resp_bits_data_vec;
219+
(void)finished_ptr;
220+
cyclotron_tile_tick_rs();
221+
}
222+
174223
void cyclotron_backend_rs(
175224
uint8_t issue_valid,
176225
uint8_t issue_warp_id,

‎src/main/resources/vsrc/CyclotronTile.v‎

Lines changed: 225 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,225 @@
1+
module CyclotronTile #(
2+
parameter ARCH_LEN = 32,
3+
parameter INST_BITS = 64,
4+
parameter IMEM_TAG_BITS = 32,
5+
parameter DMEM_DATA_BITS = 32,
6+
parameter DMEM_TAG_BITS = 32,
7+
parameter NUM_WARPS = 8,
8+
parameter NUM_LANES = 16,
9+
parameter OP_BITS = 9,
10+
parameter REG_BITS = 8,
11+
parameter IMM_BITS = 32,
12+
parameter CSR_IMM_BITS = 8,
13+
parameter PRED_BITS = 4,
14+
localparam DMEM_SIZE_BITS = $clog2($clog2(DMEM_DATA_BITS / 8) + 1),
15+
localparam DMEM_MASK_BITS = (DMEM_DATA_BITS / 8),
16+
localparam OPNOEXT_BITS = 7,
17+
localparam OPEXT_BITS = 2,
18+
localparam WARP_ID_BITS = $clog2(NUM_WARPS),
19+
localparam WARP_COUNT_BITS = $clog2(NUM_WARPS+1)
20+
) (
21+
input clock,
22+
input reset,
23+
24+
output logic imem_req_valid,
25+
input logic imem_req_ready,
26+
output logic [ARCH_LEN-1:0] imem_req_bits_address,
27+
output logic [IMEM_TAG_BITS-1:0] imem_req_bits_tag,
28+
output logic imem_resp_ready,
29+
input logic imem_resp_valid,
30+
input logic [IMEM_TAG_BITS-1:0] imem_resp_bits_tag,
31+
input logic [INST_BITS-1:0] imem_resp_bits_data,
32+
33+
output logic [NUM_LANES-1:0] dmem_req_valid,
34+
input logic [NUM_LANES-1:0] dmem_req_ready,
35+
output logic [NUM_LANES-1:0] dmem_req_bits_store,
36+
output logic [(NUM_LANES*DMEM_TAG_BITS)-1:0] dmem_req_bits_tag,
37+
output logic [(NUM_LANES*ARCH_LEN)-1:0] dmem_req_bits_address,
38+
output logic [(NUM_LANES*DMEM_SIZE_BITS)-1:0] dmem_req_bits_size,
39+
output logic [(NUM_LANES*DMEM_DATA_BITS)-1:0] dmem_req_bits_data,
40+
output logic [(NUM_LANES*DMEM_MASK_BITS)-1:0] dmem_req_bits_mask,
41+
output logic [NUM_LANES-1:0] dmem_resp_ready,
42+
input logic [NUM_LANES-1:0] dmem_resp_valid,
43+
input logic [(NUM_LANES*DMEM_TAG_BITS)-1:0] dmem_resp_bits_tag,
44+
input logic [(NUM_LANES*DMEM_DATA_BITS)-1:0] dmem_resp_bits_data,
45+
output logic finished
46+
);
47+
`include "Cyclotron.vh"
48+
49+
import "DPI-C" function void cyclotron_tile_tick(
50+
output bit imem_req_valid,
51+
input bit imem_req_ready,
52+
output int imem_req_bits_address,
53+
output longint imem_req_bits_tag,
54+
output bit imem_resp_ready,
55+
input bit imem_resp_valid,
56+
input longint imem_resp_bits_tag,
57+
input longint imem_resp_bits_data,
58+
output bit dmem_req_valid[NUM_LANES],
59+
input bit dmem_req_ready[NUM_LANES],
60+
output bit dmem_req_bits_store[NUM_LANES],
61+
output int dmem_req_bits_address[NUM_LANES],
62+
output byte dmem_req_bits_size[NUM_LANES],
63+
output int dmem_req_bits_tag[NUM_LANES],
64+
output int dmem_req_bits_data[NUM_LANES],
65+
output byte dmem_req_bits_mask[NUM_LANES],
66+
output bit dmem_resp_ready[NUM_LANES],
67+
input bit dmem_resp_valid[NUM_LANES],
68+
input int dmem_resp_bits_tag[NUM_LANES],
69+
input int dmem_resp_bits_data[NUM_LANES],
70+
output bit finished
71+
);
72+
73+
initial cyclotron_init_task();
74+
75+
bit __out_imem_req_ready;
76+
bit __out_imem_resp_valid;
77+
longint __out_imem_resp_bits_tag;
78+
longint __out_imem_resp_bits_data;
79+
80+
bit __in_imem_req_valid;
81+
int __in_imem_req_bits_address;
82+
longint __in_imem_req_bits_tag;
83+
bit __in_imem_resp_ready;
84+
bit __in_imem_req_valid_next;
85+
int __in_imem_req_bits_address_next;
86+
longint __in_imem_req_bits_tag_next;
87+
bit __in_imem_resp_ready_next;
88+
89+
bit __in_finished;
90+
bit __in_finished_next;
91+
92+
bit __out_dmem_req_ready [0:NUM_LANES-1];
93+
bit __out_dmem_resp_valid[0:NUM_LANES-1];
94+
int __out_dmem_resp_tag [0:NUM_LANES-1];
95+
int __out_dmem_resp_data [0:NUM_LANES-1];
96+
97+
bit __in_dmem_req_valid [0:NUM_LANES-1];
98+
bit __in_dmem_req_store [0:NUM_LANES-1];
99+
int __in_dmem_req_address [0:NUM_LANES-1];
100+
byte __in_dmem_req_size [0:NUM_LANES-1];
101+
int __in_dmem_req_tag [0:NUM_LANES-1];
102+
int __in_dmem_req_data [0:NUM_LANES-1];
103+
byte __in_dmem_req_mask [0:NUM_LANES-1];
104+
bit __in_dmem_resp_ready [0:NUM_LANES-1];
105+
106+
bit __in_dmem_req_valid_next [0:NUM_LANES-1];
107+
bit __in_dmem_req_store_next [0:NUM_LANES-1];
108+
int __in_dmem_req_address_next [0:NUM_LANES-1];
109+
byte __in_dmem_req_size_next [0:NUM_LANES-1];
110+
int __in_dmem_req_tag_next [0:NUM_LANES-1];
111+
int __in_dmem_req_data_next [0:NUM_LANES-1];
112+
byte __in_dmem_req_mask_next [0:NUM_LANES-1];
113+
bit __in_dmem_resp_ready_next [0:NUM_LANES-1];
114+
115+
assign __out_imem_req_ready = imem_req_ready;
116+
assign __out_imem_resp_valid = imem_resp_valid;
117+
assign __out_imem_resp_bits_tag = imem_resp_bits_tag;
118+
assign __out_imem_resp_bits_data = imem_resp_bits_data;
119+
120+
assign imem_req_valid = __in_imem_req_valid;
121+
assign imem_req_bits_address = __in_imem_req_bits_address[ARCH_LEN-1:0];
122+
assign imem_req_bits_tag = __in_imem_req_bits_tag[IMEM_TAG_BITS-1:0];
123+
assign imem_resp_ready = __in_imem_resp_ready;
124+
125+
assign finished = __in_finished;
126+
127+
genvar g;
128+
generate
129+
for (g = 0; g < NUM_LANES; g = g + 1) begin
130+
assign __out_dmem_req_ready[g] = dmem_req_ready[g];
131+
assign __out_dmem_resp_valid[g] = dmem_resp_valid[g];
132+
assign __out_dmem_resp_tag[g] = dmem_resp_bits_tag[DMEM_TAG_BITS*g +: DMEM_TAG_BITS];
133+
assign __out_dmem_resp_data[g] = dmem_resp_bits_data[DMEM_DATA_BITS*g +: DMEM_DATA_BITS];
134+
135+
assign dmem_req_valid[g] = __in_dmem_req_valid[g];
136+
assign dmem_req_bits_store[g] = __in_dmem_req_store[g];
137+
assign dmem_req_bits_address[ARCH_LEN*g +: ARCH_LEN] =
138+
__in_dmem_req_address[g][ARCH_LEN-1:0];
139+
assign dmem_req_bits_size[DMEM_SIZE_BITS*g +: DMEM_SIZE_BITS] =
140+
__in_dmem_req_size[g][DMEM_SIZE_BITS-1:0];
141+
assign dmem_req_bits_tag[DMEM_TAG_BITS*g +: DMEM_TAG_BITS] =
142+
__in_dmem_req_tag[g][DMEM_TAG_BITS-1:0];
143+
assign dmem_req_bits_data[DMEM_DATA_BITS*g +: DMEM_DATA_BITS] =
144+
__in_dmem_req_data[g][DMEM_DATA_BITS-1:0];
145+
assign dmem_req_bits_mask[DMEM_MASK_BITS*g +: DMEM_MASK_BITS] =
146+
__in_dmem_req_mask[g][DMEM_MASK_BITS-1:0];
147+
assign dmem_resp_ready[g] = __in_dmem_resp_ready[g];
148+
end
149+
endgenerate
150+
151+
always @(posedge clock) begin
152+
if (reset) begin
153+
__in_imem_req_valid <= '0;
154+
__in_imem_req_bits_address <= '0;
155+
__in_imem_req_bits_tag <= '0;
156+
__in_imem_resp_ready <= '0;
157+
__in_finished <= '0;
158+
for (integer i = 0; i < NUM_LANES; i = i + 1) begin
159+
__in_dmem_req_valid[i] <= '0;
160+
__in_dmem_req_store[i] <= '0;
161+
__in_dmem_req_address[i] <= '0;
162+
__in_dmem_req_size[i] <= '0;
163+
__in_dmem_req_tag[i] <= '0;
164+
__in_dmem_req_data[i] <= '0;
165+
__in_dmem_req_mask[i] <= '0;
166+
__in_dmem_resp_ready[i] <= '0;
167+
end
168+
end else begin
169+
__in_imem_req_valid_next = __in_imem_req_valid;
170+
__in_imem_req_bits_address_next = __in_imem_req_bits_address;
171+
__in_imem_req_bits_tag_next = __in_imem_req_bits_tag;
172+
__in_imem_resp_ready_next = __in_imem_resp_ready;
173+
__in_finished_next = __in_finished;
174+
for (integer i = 0; i < NUM_LANES; i = i + 1) begin
175+
__in_dmem_req_valid_next[i] = __in_dmem_req_valid[i];
176+
__in_dmem_req_store_next[i] = __in_dmem_req_store[i];
177+
__in_dmem_req_address_next[i] = __in_dmem_req_address[i];
178+
__in_dmem_req_size_next[i] = __in_dmem_req_size[i];
179+
__in_dmem_req_tag_next[i] = __in_dmem_req_tag[i];
180+
__in_dmem_req_data_next[i] = __in_dmem_req_data[i];
181+
__in_dmem_req_mask_next[i] = __in_dmem_req_mask[i];
182+
__in_dmem_resp_ready_next[i] = __in_dmem_resp_ready[i];
183+
end
184+
cyclotron_tile_tick(
185+
__in_imem_req_valid_next,
186+
__out_imem_req_ready,
187+
__in_imem_req_bits_address_next,
188+
__in_imem_req_bits_tag_next,
189+
__in_imem_resp_ready_next,
190+
__out_imem_resp_valid,
191+
__out_imem_resp_bits_tag,
192+
__out_imem_resp_bits_data,
193+
__in_dmem_req_valid_next,
194+
__out_dmem_req_ready,
195+
__in_dmem_req_store_next,
196+
__in_dmem_req_address_next,
197+
__in_dmem_req_size_next,
198+
__in_dmem_req_tag_next,
199+
__in_dmem_req_data_next,
200+
__in_dmem_req_mask_next,
201+
__in_dmem_resp_ready_next,
202+
__out_dmem_resp_valid,
203+
__out_dmem_resp_tag,
204+
__out_dmem_resp_data,
205+
__in_finished_next
206+
);
207+
__in_imem_req_valid <= __in_imem_req_valid_next;
208+
__in_imem_req_bits_address <= __in_imem_req_bits_address_next;
209+
__in_imem_req_bits_tag <= __in_imem_req_bits_tag_next;
210+
__in_imem_resp_ready <= __in_imem_resp_ready_next;
211+
__in_finished <= __in_finished_next;
212+
for (integer i = 0; i < NUM_LANES; i = i + 1) begin
213+
__in_dmem_req_valid[i] <= __in_dmem_req_valid_next[i];
214+
__in_dmem_req_store[i] <= __in_dmem_req_store_next[i];
215+
__in_dmem_req_address[i] <= __in_dmem_req_address_next[i];
216+
__in_dmem_req_size[i] <= __in_dmem_req_size_next[i];
217+
__in_dmem_req_tag[i] <= __in_dmem_req_tag_next[i];
218+
__in_dmem_req_data[i] <= __in_dmem_req_data_next[i];
219+
__in_dmem_req_mask[i] <= __in_dmem_req_mask_next[i];
220+
__in_dmem_resp_ready[i] <= __in_dmem_resp_ready_next[i];
221+
end
222+
end
223+
end
224+
225+
endmodule

‎src/main/scala/radiance/muon/MuonCore.scala‎

Lines changed: 10 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -275,6 +275,10 @@ abstract class CoreModule(implicit val p: Parameters) extends Module
275275
abstract class CoreBundle(implicit val p: Parameters) extends ParameterizedBundle()(p)
276276
with HasCoreParameters
277277

278+
/** Data memory interface for the core.
279+
* The interface is per-lane, with each lane being word-size-wide with its own
280+
* tag and ready/valid. The coalescer at downstream is responsible for merging
281+
* them into wide reqs when possible. */
278282
class DataMemIO(implicit p: Parameters) extends CoreBundle()(p) {
279283
val req = Vec(
280284
muonParams.lsu.numLsuLanes,
@@ -286,6 +290,8 @@ class DataMemIO(implicit p: Parameters) extends CoreBundle()(p) {
286290
)
287291
}
288292

293+
/** Shared memory interface for the core.
294+
* Per-lane similar to DataMemIO. */
289295
class SharedMemIO(implicit p: Parameters) extends CoreBundle()(p) {
290296
val req = Vec(
291297
muonParams.lsu.numLsuLanes,
@@ -297,6 +303,9 @@ class SharedMemIO(implicit p: Parameters) extends CoreBundle()(p) {
297303
)
298304
}
299305

306+
/** Instruction memory interface for the core.
307+
* The interface is a single, instruction-length-wide lane, serving all lanes
308+
* in the backend via SIMD. */
300309
class InstMemIO(implicit val p: Parameters) extends ParameterizedBundle()(p) with HasCoreParameters {
301310
val req = Decoupled(new MemRequest(
302311
tagBits = imemTagBits,
@@ -314,7 +323,7 @@ class PerfIO()(implicit p: Parameters) extends CoreBundle()(p) {
314323
}
315324

316325
/** Trace IO to software testbench that logs PC and register read data at
317-
* issue time. */
326+
* issue time. */
318327
class TraceIO()(implicit p: Parameters) extends CoreBundle()(p) {
319328
val pc = pcT
320329
val warpId = widT

‎src/main/scala/radiance/muon/ReservationStation.scala‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -458,7 +458,7 @@ class ReservationStation(implicit p: Parameters) extends CoreModule()(p) {
458458
when (valid) {
459459
val uop = instTable(i).uop
460460
debugf(cf"${i} | warp:${uop.wid} | pc:0x${uop.pc}%x | " +
461-
cf"regs: [rd:${uop.inst.rd} rs1:${uop.inst.rs1} rs2:${uop.inst.rs2} rs3:${uop.inst.rs3}] | " +
461+
cf"[rd:${uop.inst.rd} rs1:${uop.inst.rs1} rs2:${uop.inst.rs2} rs3:${uop.inst.rs3}] | " +
462462
cf"hasOp:${hasOpTable(i)(0)}${hasOpTable(i)(1)}${hasOpTable(i)(2)} | " +
463463
cf"opReady:${opReadyTable(i)(0)}${opReadyTable(i)(1)}${opReadyTable(i)(2)} | " +
464464
cf"busy:${busyTable(i)(0)}${busyTable(i)(1)}${busyTable(i)(2)} | " +

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