Parameterize LSQ depth to toplevel configs

Author: hansungk

chipyard/RadianceConfigs.scala

@@ -246,7 +246,8 @@ class RadianceSingleClusterIssueDepthConfig(issueQueueEntries: Int) extends Conf
     noILP = false,
     l0i = Some(L0iCacheConfig),
     l0d = Some(L0dCacheConfig),
-    profiler = false,
+    trace = true,
+    profiler = true,
     numIssueQueueEntries = issueQueueEntries
   ) ++
   new WithRadianceCluster(0, smemConfig = TapeoutSmemConfig, l1Config = L1CacheConfig) ++
@@ -263,6 +264,30 @@ class RadianceSingleClusterIssueDepth8Config extends RadianceSingleClusterIssueD
 class RadianceSingleClusterIssueDepth16Config extends RadianceSingleClusterIssueDepthConfig(16)
 class RadianceSingleClusterIssueDepth32Config extends RadianceSingleClusterIssueDepthConfig(32)
 
+class RadianceSingleClusterLSQDepthConfig(lsqDepth: Int) extends Config(
+  new WithMuonCores(
+    2,
+    location = InCluster(0),
+    noILP = false,
+    l0i = Some(L0iCacheConfig),
+    l0d = Some(L0dCacheConfig),
+    profiler = false,
+    lsqDepth = Some(lsqDepth)
+  ) ++
+  new WithRadianceCluster(0, smemConfig = TapeoutSmemConfig, l1Config = L1CacheConfig) ++
+  new WithExtGPUMem() ++
+  new WithRadianceRocket ++
+  new WithGPUResetAggregator(defaultReset = false) ++
+  new RadianceBaseConfig
+)
+
+class RadianceSingleClusterLSQDepth1Config extends RadianceSingleClusterLSQDepthConfig(1)
+class RadianceSingleClusterLSQDepth2Config extends RadianceSingleClusterLSQDepthConfig(2)
+class RadianceSingleClusterLSQDepth4Config extends RadianceSingleClusterLSQDepthConfig(4)
+class RadianceSingleClusterLSQDepth8Config extends RadianceSingleClusterLSQDepthConfig(8)
+class RadianceSingleClusterLSQDepth16Config extends RadianceSingleClusterLSQDepthConfig(16)
+class RadianceSingleClusterLSQDepth32Config extends RadianceSingleClusterLSQDepthConfig(32)
+
 object RadianceWarpLenConfig {
   private val minL0dLineBytes = 64
   private val wordBytes = 32 / 8

src/main/scala/radiance/muon/LSU.scala

@@ -32,6 +32,18 @@ case class LoadStoreUnitParams(
     val smemDoesntReorder: Boolean = true, // see comment above LSQMemUpdate
     val fastHeadUpdate: Boolean = true,    // allow logical head to update on same cycle as memUpdate / memResponse
 ) {
+    private val depths = Seq(
+        numGlobalLdqEntries,
+        numGlobalStqEntries,
+        numSharedLdqEntries,
+        numSharedStqEntries,
+        loadDataEntries,
+        storeDataEntries,
+        addressEntries,
+    )
+    require(depths.forall(_ > 0), "LSU queue depths must be positive")
+    require(depths.forall(isPow2(_)), "LSU queue depths must be powers of two")
+
     val globalLdqIndexBits = log2Up(numGlobalLdqEntries)
     val globalStqIndexBits = log2Up(numGlobalStqEntries)
     val globalLdqCircIndexBits = globalLdqIndexBits + 1
@@ -49,6 +61,38 @@ case class LoadStoreUnitParams(
     val addressIdxBits = log2Up(addressEntries)
 }
 
+case class LoadStoreUnitDepthOverrides(
+    numGlobalLdqEntries: Option[Int] = None,
+    numGlobalStqEntries: Option[Int] = None,
+    numSharedLdqEntries: Option[Int] = None,
+    numSharedStqEntries: Option[Int] = None,
+    loadDataEntries: Option[Int] = None,
+    storeDataEntries: Option[Int] = None,
+    addressEntries: Option[Int] = None,
+) {
+    def applyTo(lsu: LoadStoreUnitParams): LoadStoreUnitParams = lsu.copy(
+        numGlobalLdqEntries = numGlobalLdqEntries.getOrElse(lsu.numGlobalLdqEntries),
+        numGlobalStqEntries = numGlobalStqEntries.getOrElse(lsu.numGlobalStqEntries),
+        numSharedLdqEntries = numSharedLdqEntries.getOrElse(lsu.numSharedLdqEntries),
+        numSharedStqEntries = numSharedStqEntries.getOrElse(lsu.numSharedStqEntries),
+        loadDataEntries = loadDataEntries.getOrElse(lsu.loadDataEntries),
+        storeDataEntries = storeDataEntries.getOrElse(lsu.storeDataEntries),
+        addressEntries = addressEntries.getOrElse(lsu.addressEntries),
+    )
+}
+
+object LoadStoreUnitDepthOverrides {
+    def all(depth: Int): LoadStoreUnitDepthOverrides = LoadStoreUnitDepthOverrides(
+        numGlobalLdqEntries = Some(depth),
+        numGlobalStqEntries = Some(depth),
+        numSharedLdqEntries = Some(depth),
+        numSharedStqEntries = Some(depth),
+        loadDataEntries = Some(depth),
+        storeDataEntries = Some(depth),
+        addressEntries = Some(depth),
+    )
+}
+
 case object MuonLoadStoreUnitDebugIdKey extends Field[Option[Int]](None)
 
 class LoadStoreUnitDerivedParams(

src/main/scala/radiance/subsystem/Configs.scala

@@ -21,7 +21,6 @@ import radiance.muon._
 import radiance.muon.backend.fp.FPPipeParams
 import radiance.muon.backend.int.IntPipeParams
 import radiance.virgo.{NumVortexCores, VirgoClusterParams, VortexCoreParams, VortexL1Key}
-import radiance.muon.LoadStoreUnitParams
 import radiance.unittest.CyclotronLinked
 
 sealed trait RadianceSmemSerialization
@@ -78,6 +77,7 @@ class WithMuonCores(
   numLanes: Option[Int],
   numPhysRegs: Option[Int],
   numIssueQueueEntries: Int,
+  lsqDepth: Option[Int],
   l0i: Option[DCacheParams],
   l0d: Option[DCacheParams],
 ) extends Config((site, here, up) => {
@@ -101,6 +101,12 @@ class WithMuonCores(
         numFP16ExpLanes = (lanes / 4).max(1)
       )
     }
+    val lsu = MuonCoreParams().lsu.copy(
+      numLsuLanes = numLanes.getOrElse(simt.numLsuLanes)
+    )
+    val resolvedLsu = lsqDepth
+      .map(depth => LoadStoreUnitDepthOverrides.all(depth).applyTo(lsu))
+      .getOrElse(lsu)
     MuonCoreParams(
       numWarps = resolvedNumWarps,
       numLanes = resolvedNumLanes,
@@ -115,9 +121,7 @@ class WithMuonCores(
       // for muon, numSMEMInFlights controlled by lsu parameters, rather than 
       // from SIMTCoreParams. TODO: use SIMTCoreParams instead?
       // logSMEMInFlights = log2Ceil(up(SIMTCoreKey).get.numSMEMInFlights),
-      lsu = LoadStoreUnitParams(
-        numLsuLanes = numLanes.getOrElse(simt.numLsuLanes)
-      ),
+      lsu = resolvedLsu,
       trace = trace || difftest,
       profiler = profiler,
       difftest = difftest,
@@ -171,6 +175,7 @@ class WithMuonCores(
     numLanes: Option[Int] = None,
     numPhysRegs: Option[Int] = None,
     numIssueQueueEntries: Int = 8,
+    lsqDepth: Option[Int] = None,
     l0i: Option[DCacheParams] = None, l0d: Option[DCacheParams] = None)
   = this(n, location, RocketCrossingParams(
     master = HierarchicalElementMasterPortParams.locationDefault(location),
@@ -179,7 +184,7 @@ class WithMuonCores(
       case InSubsystem => CBUS
       case InCluster(clusterId) => CCBUS(clusterId)
     },
-  ), standalone, noILP, trace, profiler, cyclotron, difftest, disabled, numWarps, numLanes, numPhysRegs, numIssueQueueEntries, l0i, l0d)
+  ), standalone, noILP, trace, profiler, cyclotron, difftest, disabled, numWarps, numLanes, numPhysRegs, numIssueQueueEntries, lsqDepth, l0i, l0d)
 }
 
 class WithCyclotronCores(