@@ -617,6 +617,7 @@ class ROB(val parameter: ROBParameter) extends Module with SerializableModule[RO
617617 io.writeBackData.lsuWriteBack.ready := true .B
618618
619619 val intrNoReg = RegInit (0 .U (13 .W ))
620+ val sampleInt = Wire (Bool ())
620621 def shouldCommitException (idx : UInt ): Bool =
621622 exceptionInfo(idx).ecodes === ECodes .SYS ||
622623 exceptionInfo(idx).ecodes === ECodes .BRK
@@ -626,6 +627,7 @@ class ROB(val parameter: ROBParameter) extends Module with SerializableModule[RO
626627 valid(deqPtr.value) &&
627628 writeBacked(deqPtr.value) &&
628629 (robState === s_normal || robState === s_idle) &&
630+ sampleInt &&
629631 io.lsuCanCommit // hasException 只会存在一个周期,这一个周期会commit掉syscall指令,并将状态转移到exception状态
630632 /** 4.Commit */
631633 val commit = Wire (
@@ -829,14 +831,14 @@ class ROB(val parameter: ROBParameter) extends Module with SerializableModule[RO
829831 io.icacheOpBranchInfo.bits.isRet := false .B
830832 }
831833 // [Interrupt]
834+ sampleInt := false .B
832835 intrCanCommit := true .B
833836 val intrNo =
834837 io.intrInfo.estat.is_12 ## io.intrInfo.estat.is_11 ## io.intrInfo.estat.zero1 ## io.intrInfo.estat.is_9_2 ## io.intrInfo.estat.is_1_0
835838 when(intrNo =/= 0 .U && canSampleIntr && io.intrInfo.ie) { // lock the first intr i meet
836839 when(
837840 valid(deqPtr.value) &&
838- ((! exception(deqPtr.value) &&
839- exceptionInfo(deqPtr.value).ecodes === ECodes .NONE &&
841+ ((
840842 robState === s_normal &&
841843 writeBacked(deqPtr.value) &&
842844 ! io.redirect.valid &&
@@ -845,6 +847,7 @@ class ROB(val parameter: ROBParameter) extends Module with SerializableModule[RO
845847 exception(deqPtr.value) := true .B
846848 exceptionInfo(deqPtr.value).ecodes := ECodes .INT
847849 intrNoReg := intrNo
850+ sampleInt := true .B
848851 io.intrInfo.canSampleIntr := false .B
849852 canSampleIntr := false .B // lock
850853 intrCanCommit := false .B
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