feat(lsu): add storeready

Signed-off-by: Woshiluo Luo <woshiluo.luo@outlook.com>

Author: woshiluo

rtl/src/backend/execute/fu/LsuBlock.scala

@@ -205,7 +205,7 @@ class RawLsuBlockIO(parameter: LsuBlockParameter) extends Bundle {
     Decoupled(new MemWrReq(parameter.addressWidth, parameter.bankWidth, parameter.bankCount)))
   val memWrResp = Vec(2, Flipped(Decoupled(new MemWrResp())))
 
-  val icacopOut = Valid(new ICacheOp(parameter.addressWidth))
+  val icacopOut  = Valid(new ICacheOp(parameter.addressWidth))
   val storeReady = Output(Bool())
 }
 
@@ -307,6 +307,7 @@ class AddrTransStage(parameter: LsuBlockParameter) extends Module {
     val cacheInfo =
       Output(Vec(parameter.portCount, ValidIO(new CacheInfo(parameter.pRegNum, parameter.robSize))))
     val storeCount = Input(UInt(4.W))
+    val storeReady = Output(Bool())
   })
   class AddrQueuePtr(override val entries: Int) extends CircularQueuePtr[AddrQueuePtr](entries)
 
@@ -522,9 +523,10 @@ class AddrTransStage(parameter: LsuBlockParameter) extends Module {
     io.cacheInfo(i).bits.robIdx := item.in.robIdx
   }
 
-  io.in.ready  := allQueueReady & reallyStoreCount <= 7.U
-  io.out.valid := io.out.bits.exists(x => x.valid)
-  io.noLoad    := ~io.out.bits.exists(x => x.valid)
+  io.storeReady := reallyStoreCount <= 7.U
+  io.in.ready   := allQueueReady & reallyStoreCount <= 7.U
+  io.out.valid  := io.out.bits.exists(x => x.valid)
+  io.noLoad     := ~io.out.bits.exists(x => x.valid)
 }
 
 /** Hardware Implementation of AluBlock */
@@ -560,6 +562,7 @@ class LsuBlock(val parameter: LsuBlockParameter)
   dataRWStage.io.noLoad          <> addrTransStage.io.noLoad
   io.icacopOut                   := dataRWStage.io.icacopOut
   addrTransStage.io.storeCount   := dataRWStage.io.storeCount
+  io.storeReady                  := addrTransStage.io.storeReady
   if (parameter.hasCache) {
     for (i <- 0 until 3 * parameter.portCount) {
       io.cacheInfo(i) := dataRWStage.io.cacheInfo(i)