[WIP] Explicit Top Module Mapping in Synthesis Flow

vtr_flow/benchmarks/top_modules.tcl

@@ -0,0 +1,79 @@
+namespace eval ::slang {
+	# INFO: Maps HDL files to respective top module(s) 
+	# top_map insertion syntax:
+	# <file> <top module>
+	array set top_map {
+		and_latch.v and_latch
+		multiclock_output_and_latch.v multiclock_output_and_latch
+		multiclock_reader_writer.v multiclock_reader_writer
+		multiclock_separate_and_latch.v multiclock_separate_and_latch
+		arm_core.v arm_core
+		bgm.v bgm
+		blob_merge.v RLE_BlobMerging
+		boundtop.v paj_boundtop_hierarchy_no_mem
+		ch_intrinsics.v memset
+		ch_intrinsics_modified.v memset
+		diffeq1.v diffeq_paj_convert
+		diffeq2.v diffeq_f_systemC
+		LU8PEEng.v LU8PEEng
+		LU32PEEng.v LU32PEEng
+		LU64PEEng.v LU64PEEng
+		mcml.v mcml
+		mkDelayWorker32B.v mkDelayWorker32B
+		mkPktMerge.v mkPktMerge
+		mkSMAdapter4B.v mkSMAdapter4B
+		or1200.v or1200_flat
+		raygentop.v paj_raygentop_hierarchy_no_mem
+		sha.v sha1
+		stereovision0.v sv_chip0_hierarchy_no_mem
+		stereovision1.v sv_chip1_hierarchy_no_mem
+		stereovision2.v sv_chip2_hierarchy_no_mem
+		stereovision3.v sv_chip3_hierarchy_no_mem
+		button_controller.sv top
+		display_control.sv top
+		debounce.sv top
+		timer.sv top
+		deepfreeze.style1.sv top
+		pulse_led.v top
+		clock.sv top
+		single_ff.v top
+		single_wire.v top
+		PWM.v top
+		flattened_pulse_width_led.sv top
+		modify_count.sv top
+		time_counter.sv top
+		spree.v system
+		attention_layer.v attention_layer
+		bnn.v bnn
+		tpu_like.small.os.v top
+		tpu_like.small.ws.v top
+		dla_like.small.v DLA
+		conv_layer_hls.v top
+		conv_layer.v conv_layer
+		eltwise_layer.v eltwise_layer
+		robot_rl.v robot_maze
+		reduction_layer.v reduction_layer
+		spmv.v spmv
+		softmax.v softmax
+		test.v top
+		mult_9x9.v mult_nxn
+		mult_8x8.v mult_nxn
+		mult_7x7.v mult_nxn
+		mult_6x6.v mult_nxn
+		mult_5x5.v mult_nxn
+		mult_4x4.v mult_nxn
+		mm3.v mm3
+		d_flip_flop.v d_flip_flop
+	}
+	# INFO: List of HDL includes files 
+	# includes_map insertion syntax:
+	# <file> include
+	array set includes_map {
+		hard_block_include.v include
+		complex_dsp_include.v include
+		hard_mem_include.v include
+		generic_definitions1.vh include
+		generic_definitions2.vh include
+		memory_controller.v include
+	}
+}

vtr_flow/misc/yosys/slang_filelist.tcl

@@ -7,71 +7,10 @@
 
 
 namespace eval ::slang {
-	# INFO: Maps HDL files to respective top module(s) 
-	# top_map insertion syntax:
-	# <file> <top module>
-	array set top_map {
-		and_latch.v and_latch
-		multiclock_output_and_latch.v multiclock_output_and_latch
-		multiclock_reader_writer.v multiclock_reader_writer
-		multiclock_separate_and_latch.v multiclock_separate_and_latch
-		arm_core.v arm_core
-		bgm.v bgm
-		blob_merge.v RLE_BlobMerging
-		boundtop.v paj_boundtop_hierarchy_no_mem
-		ch_intrinsics.v memset
-		diffeq1.v diffeq_paj_convert
-		diffeq2.v diffeq_f_systemC
-		LU8PEEng.v LU8PEEng
-		LU32PEEng.v LU32PEEng
-		LU64PEEng.v LU64PEEng
-		mcml.v mcml
-		mkDelayWorker32B.v mkDelayWorker32B
-		mkPktMerge.v mkPktMerge
-		mkSMAdapter4B.v mkSMAdapter4B
-		or1200.v or1200_flat
-		raygentop.v paj_raygentop_hierarchy_no_mem
-		sha.v sha1
-		stereovision0.v sv_chip0_hierarchy_no_mem
-		stereovision1.v sv_chip1_hierarchy_no_mem
-		stereovision2.v sv_chip2_hierarchy_no_mem
-		stereovision3.v sv_chip3_hierarchy_no_mem
-		button_controller.sv top
-		display_control.sv top
-		debounce.sv top
-		timer.sv top
-		deepfreeze.style1.sv top
-		pulse_led.v top
-		clock.sv top
-		single_ff.v top
-		single_wire.v top
-		PWM.v top
-		flattened_pulse_width_led.sv top
-		modify_count.sv top
-		time_counter.sv top
-		spree.v system
-		attention_layer.v attention_layer
-		bnn.v bnn
-		tpu_like.small.os.v top
-		tpu_like.small.ws.v top
-		dla_like.small.v DLA
-		conv_layer_hls.v top
-		conv_layer.v conv_layer
-		eltwise_layer.v eltwise_layer
-		robot_rl.v robot_maze
-		reduction_layer.v reduction_layer
-		spmv.v spmv
-		softmax.v softmax
-	}
-	# INFO: List of HDL includes files 
-	# includes_map insertion syntax:
-	# <file> include
-	array set includes_map {
-		hard_block_include.v include
-	}
 
 
-	variable top_args {}
+	variable top_mods_slang {}
+	variable top_mods_verilog {}
 
 # Function - build_filelist:
 #
@@ -85,11 +24,14 @@ namespace eval ::slang {
 #	file_list - text file being written to that will contain
 #	     		the names of circuits from circuit list.
 #
-	proc build_filelist { circuit_list file_list } {
-		variable top_args
+	proc build_filelist { circuit_list file_list tops_path} {
+		variable top_mods_slang
+		variable top_mods_verilog
 		variable top_map
 		variable includes_map
-		set top_args {}
+		source [file join [pwd] "$tops_path"]
+		set top_mods_slang {}
+		set top_mods_verilog {}
 		set fh [open $file_list "w"]
 		foreach f $circuit_list {
 			set ext [string tolower [file extension $f]]
@@ -105,7 +47,8 @@ namespace eval ::slang {
 					} else {
 						puts $fh $f
 						set top_name $top_map($f)
-						lappend top_args --top $top_name
+						lappend top_mods_slang --top $top_name
+						lappend top_mods_verilog -top $top_name
 					}
 				}
 			} else {
@@ -114,6 +57,6 @@ namespace eval ::slang {
 			}
 		}
 		close $fh
-		return $top_args
+		return [list $top_mods_slang $top_mods_verilog]
 	}
 }

vtr_flow/misc/yosys/synthesis.tcl

@@ -28,16 +28,20 @@ if {$env(PARSER) == "slang" } {
 
 parmys_arch -a QQQ
 
+variable HDL_tops
+
+# Create a file list containing the name(s) of file(s) \
+# to read together with read_slang
+source [file join [pwd] "slang_filelist.tcl"]
+set readfile [file join [pwd] "filelist.txt"]
+#Writing names of circuit files to file list
+set HDL_tops [::slang::build_filelist {XXX} $readfile $env(TOPS)]
+lassign $HDL_tops top_mods_slang top_mods_verilog
+
 if {$env(PARSER) == "slang" } {
-	# Create a file list containing the name(s) of file(s) \
-	# to read together with read_slang
-	source [file join [pwd] "slang_filelist.tcl"]
-	set readfile [file join [pwd] "filelist.txt"]
-	#Writing names of circuit files to file list
-	set slang_tops [::slang::build_filelist {XXX} $readfile]
 	puts "Using Yosys read_slang command"
 	#Read vtr_primitives library and user design verilog in same command
-	read_slang -v $env(PRIMITIVES) {*}$slang_tops -C $readfile
+	read_slang -v $env(PRIMITIVES) {*}$top_mods_slang -C $readfile
 } elseif {$env(PARSER) == "default" } {
 	puts "Using Yosys read_verilog command"
 	read_verilog -nomem2reg +/parmys/vtr_primitives.v
@@ -53,7 +57,8 @@ scc -select
 select -assert-none %
 select -clear
 
-hierarchy -check -auto-top -purge_lib
+#hierarchy -check -auto-top -purge_lib
+hierarchy -check {*}$top_mods_verilog -purge_lib
 
 opt_expr
 opt_clean
@@ -97,6 +102,7 @@ opt -fast -noff
 
 stat
 
-hierarchy -check -auto-top -purge_lib
+#hierarchy -check -auto-top -purge_lib
+hierarchy -check {*}$top_mods_verilog -purge_lib
 
 write_blif -true + vcc -false + gnd -undef + unconn -blackbox ZZZ

vtr_flow/scripts/python_libs/vtr/parmys/parmys.py

@@ -252,6 +252,7 @@ def run(
     if parmys_args["parser"] in YOSYS_PARSERS:
         os.environ["PARSER"] = parmys_args["parser"]
         os.environ["PRIMITIVES"] = str(vtr.paths.vtr_primitives_path)
+        os.environ["TOPS"] = str(vtr.paths.HDL_top_mods_path)
         del parmys_args["parser"]
     else:
         raise vtr.VtrError(

vtr_flow/scripts/python_libs/vtr/paths.py

@@ -8,7 +8,7 @@
 # VTR Paths
 vtr_flow_path = root_path / "vtr_flow"
 vtr_primitives_path = root_path / "build" / "share" / "yosys" / "parmys" / "vtr_primitives.v"
-
+HDL_top_mods_path = root_path / "vtr_flow" / "benchmarks" / "top_modules.tcl"
 # ODIN paths
 odin_path = root_path / "odin_ii"
 odin_exe_path = odin_path / "odin_ii"