[WIP][Place] Fixed Issue Where Macros Were Not Being Created - #3519
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AlexandreSinger wants to merge 2 commits into
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[WIP][Place] Fixed Issue Where Macros Were Not Being Created#3519AlexandreSinger wants to merge 2 commits into
AlexandreSinger wants to merge 2 commits into
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For special architectures, there may exist direct connections from one sub-tile to another within the same tile. For blocks which use these direct connections, they must be placed relative to specific constraints. Normally, to enforce these constraints during packing we use macros; however macros were not being created for this case. Although the tests were passing, they were passing due to random chance (since the initial placer happened to place them in the correct order and the annealer did not change them). Now that AP is coming in, this is actually causing an issue. Fixed the macro creation code so it actually creates a macro for this case.
vaughnbetz
reviewed
Jun 2, 2026
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| // Pure-source macro detection: | ||
| // Handles blocks that have DRIVER pins for a direct but no RECEIVER pins for that | ||
| // same direct (e.g. a multiplier driving memory blocks via sub-tile direct connections). |
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- This is a very long routine. Suggest adding some helper functions to break it up.
- It's not clear to me what a 'pure-source' macro is (maybe spans two different types of blocks?), or what the overall algorithm is fo identifying them. I suggest definiing the term, and giving an overview of the algorithm here,
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I agree, this was the PR I was discussing with you a week or two ago. It fixes the issue of the inter-sub-tile macros; however I am not confident in the quality of the solution (Claude had a heavy hand in creating it). I left this PR open for @amin1377 to look at if he was curious.
I did verify that it fixes the issue without breaking the rest of VPR (as far as I can tell); but the code is a bit magical.
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Ok, to @amin1377 to see if he can make a better solution.
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For special architectures, there may exist direct connections from one sub-tile to another within the same tile. For blocks which use these direct connections, they must be placed relative to specific constraints.
Normally, to enforce these constraints during packing we use macros; however macros were not being created for this case. Although the tests were passing, they were passing due to random chance (since the initial placer happened to place them in the correct order and the annealer did not change them). Now that AP is coming in, this is actually causing an issue.
Fixed the macro creation code so it actually creates a macro for this case.