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[WIP][Tatum] Added routing delays from master to generated clocks - #3614

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[WIP][Tatum] Added routing delays from master to generated clocks#3614
AlexandreSinger wants to merge 3 commits into
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feature-sdc-routed-generated-clock

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From verifying the output of Tatum and OpenSTA, I found that for generated clocks, OpenSTA usually includes the delays from the master clocks to the generated clocks in the timing paths; however, in Tatum we were not doing that.

This exposes a limitation in Tatum that we need to start our traverals at nodes with no incoming edges (so they end up at level 0 of the traversal). To support generated clocks logically, we would have to start our traversal at the master clock and then through the generated clock source; but that can be very messy and intrusive.

We can get around this by disabling the timing edges leading into the generated clock node. This ensures it is at level 0. We can then account for the delay from the master clock by adding latency to the generated clock node equal to the path delay. This ensures that the analysis is efficient and correct.

It may be confusing for the user if adding generated clocks implicitly added clock latency (even though it is equivalent), so I also updated the timing reports to reconstruct the path from the master clock to the generated clock. From the user's perspective, they would not know that we did this small optimization.

I have added strong tests to ensure that this is working for routed clocks, as well as when there are clock latencies as well.

From verifying the output of Tatum and OpenSTA, I found that for
generated clocks, OpenSTA usually includes the delays from the master
clocks to the generated clocks in the timing paths; however, in Tatum we
were not doing that.

This exposes a limitation in Tatum that we need to start our traverals
at nodes with no incoming edges (so they end up at level 0 of the
traversal). To support generated clocks logically, we would have to
start our traversal at the master clock and then through the generated
clock source; but that can be very messy and intrusive.

We can get around this by disabling the timing edges leading into the
generated clock node. This ensures it is at level 0. We can then account
for the delay from the master clock by adding latency to the generated
clock node equal to the path delay. This ensures that the analysis is
efficient and correct.

It may be confusing for the user if adding generated clocks implicitly
added clock latency (even though it is equivalent), so I also updated
the timing reports to reconstruct the path from the master clock to the
generated clock. From the user's perspective, they would not know that
we did this small optimization.

I have added strong tests to ensure that this is working for routed
clocks, as well as when there are clock latencies as well.
@github-actions github-actions Bot added VPR VPR FPGA Placement & Routing Tool docs Documentation lang-cpp C/C++ code external_libs lang-netlist labels Jun 10, 2026
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