Fix yoyo and flat router collision

vpr/src/route/connection_router.tpp

@@ -232,8 +232,6 @@ float ConnectionRouter<Heap>::compute_node_cost_using_rcv(const t_conn_cost_para
                                                           float backwards_cong,
                                                           float R_upstream) {
     const t_conn_delay_budget* delay_budget = cost_params.delay_budget;
-    // TODO: This function is not tested for is_flat == true
-    VTR_ASSERT(is_flat_ != true);
     const auto [expected_delay, expected_cong] = router_lookahead_.get_expected_delay_and_cong(to_node, target_node, cost_params, R_upstream);
 
     float expected_total_cong = expected_cong + backwards_cong;

vpr/src/route/route_budgets.cpp

@@ -370,6 +370,7 @@ float route_budgets::minimax_PERT(std::shared_ptr<SetupHoldTimingInfo> orig_timi
             // if ((size_t)net_id == 10) {
             //     VTR_LOG("NET 10 TOTAL PATH DELAY IS %e\n", total_path_delay);
             // }
+
 
             if (total_path_delay == -1) {
                 /*Delay node is not valid, leave the budgets as is*/
@@ -422,7 +423,17 @@ float route_budgets::calculate_clb_pin_slack(ParentNetId net_id,
     if (is_flat_) {
         auto curr_atom_pin = convert_to_atom_pin_id(pin);
         atom_pin = curr_atom_pin;
-        curr_min_slack = timing_info->setup_pin_slack(curr_atom_pin);
+
+        /*Get the slack according to the requested analysis type (setup vs hold).
+         *If the given pin has an infinite slack (e.g. a pin driven by a constant generator), leave
+         *the 'curr_min_slack' at its finite 'delay_upper_bound'.
+         *If the slack is finite, then we can safely assign the value to 'curr_min_slack'.
+         */
+        float pin_slack = (type == HOLD) ? timing_info->hold_pin_slack(curr_atom_pin)
+                                         : timing_info->setup_pin_slack(curr_atom_pin);
+        if (!std::isinf(pin_slack)) {
+            curr_min_slack = pin_slack;
+        }
     } else {
         /*
          *There may be multiple atom netlist pins connected to this CLB pin. Iterate through them all

vpr/src/route/router_lookahead/router_lookahead_map.cpp

@@ -206,6 +206,13 @@ float MapLookahead::get_expected_cost(RRNodeId current_node, RRNodeId target_nod
 }
 
 float MapLookahead::get_expected_cost_flat_router(RRNodeId current_node, RRNodeId target_node, const t_conn_cost_params& params, float R_upstream) const {
+    auto [delay_cost, cong_cost] = get_expected_delay_and_cong_flat_router(current_node, target_node, params, R_upstream);
+    return delay_cost + cong_cost;
+}
+
+// RCV's ConnectionRouter::compute_node_cost_using_rcv() needs the delay and congestion costs to be kept separate.
+// This function returns the two costs separately to allow flat routing to be compatible with RCV.
+std::pair<float, float> MapLookahead::get_expected_delay_and_cong_flat_router(RRNodeId current_node, RRNodeId target_node, const t_conn_cost_params& params, float R_upstream) const {
     auto& device_ctx = g_vpr_ctx.device();
     const auto& rr_graph = device_ctx.rr_graph;
 
@@ -230,22 +237,22 @@ float MapLookahead::get_expected_cost_flat_router(RRNodeId current_node, RRNodeI
     // We have not checked the multi-layer FPGA for flat routing
     VTR_ASSERT(rr_graph.node_layer_low(current_node) == rr_graph.node_layer_low(target_node));
     if (from_rr_type == e_rr_type::CHANX || from_rr_type == e_rr_type::CHANY) {
-        std::tie(delay_cost, cong_cost) = get_expected_delay_and_cong(current_node, target_node, params, R_upstream);
+        std::tie(delay_cost, cong_cost) = get_expected_delay_and_cong_global(current_node, target_node, params, R_upstream);
 
         // delay_cost and cong_cost only represent the cost to get to the root-level pins. The below offsets are used to represent the intra-cluster cost
         // of getting to a sink
         delay_offset_cost = params.criticality * tile_min_cost.at(to_physical_type->index).at(to_node_ptc_num).delay;
         cong_offset_cost = (1. - params.criticality) * tile_min_cost.at(to_physical_type->index).at(to_node_ptc_num).congestion;
 
-        return delay_cost + cong_cost + delay_offset_cost + cong_offset_cost;
+        return {delay_cost + delay_offset_cost, cong_cost + cong_offset_cost};
     } else if (from_rr_type == e_rr_type::OPIN) {
         if (is_inter_cluster_node(rr_graph, current_node)) {
             // Similar to CHANX and CHANY
-            std::tie(delay_cost, cong_cost) = get_expected_delay_and_cong(current_node, target_node, params, R_upstream);
+            std::tie(delay_cost, cong_cost) = get_expected_delay_and_cong_global(current_node, target_node, params, R_upstream);
 
             delay_offset_cost = params.criticality * tile_min_cost.at(to_physical_type->index).at(to_node_ptc_num).delay;
             cong_offset_cost = (1. - params.criticality) * tile_min_cost.at(to_physical_type->index).at(to_node_ptc_num).congestion;
-            return delay_cost + cong_cost + delay_offset_cost + cong_offset_cost;
+            return {delay_cost + delay_offset_cost, cong_cost + cong_offset_cost};
         } else {
             if (node_in_same_physical_tile(current_node, target_node)) {
                 delay_offset_cost = 0.;
@@ -258,7 +265,7 @@ float MapLookahead::get_expected_cost_flat_router(RRNodeId current_node, RRNodeI
                     // since it does not consider the cost of going outside of the cluster and, then, returning to it.
                     delay_cost = params.criticality * tile_min_cost.at(to_physical_type->index).at(to_node_ptc_num).delay;
                     cong_cost = (1. - params.criticality) * tile_min_cost.at(to_physical_type->index).at(to_node_ptc_num).congestion;
-                    return delay_cost + cong_cost;
+                    return {delay_cost, cong_cost};
                 } else {
                     delay_cost = params.criticality * pin_delay_itr->second.delay;
                     cong_cost = (1. - params.criticality) * pin_delay_itr->second.congestion;
@@ -276,7 +283,7 @@ float MapLookahead::get_expected_cost_flat_router(RRNodeId current_node, RRNodeI
                 delay_offset_cost = params.criticality * tile_min_cost.at(to_physical_type->index).at(to_node_ptc_num).delay;
                 cong_offset_cost = (1. - params.criticality) * tile_min_cost.at(to_physical_type->index).at(to_node_ptc_num).congestion;
             }
-            return delay_cost + cong_cost + delay_offset_cost + cong_offset_cost;
+            return {delay_cost + delay_offset_cost, cong_cost + cong_offset_cost};
         }
     } else if (from_rr_type == e_rr_type::IPIN) {
         // we assume that route-through is not enabled.
@@ -290,7 +297,7 @@ float MapLookahead::get_expected_cost_flat_router(RRNodeId current_node, RRNodeI
             delay_cost = params.criticality * pin_delay_itr->second.delay;
             cong_cost = (1. - params.criticality) * pin_delay_itr->second.congestion;
         }
-        return delay_cost + cong_cost;
+        return {delay_cost, cong_cost};
     } else if (from_rr_type == e_rr_type::SOURCE) {
         if (node_in_same_physical_tile(current_node, target_node)) {
             delay_cost = 0.;
@@ -307,17 +314,24 @@ float MapLookahead::get_expected_cost_flat_router(RRNodeId current_node, RRNodeI
             delay_offset_cost = params.criticality * tile_min_cost.at(to_physical_type->index).at(to_node_ptc_num).delay;
             cong_offset_cost = (1. - params.criticality) * tile_min_cost.at(to_physical_type->index).at(to_node_ptc_num).congestion;
         }
-        return delay_cost + cong_cost + delay_offset_cost + cong_offset_cost;
+        return {delay_cost + delay_offset_cost, cong_cost + cong_offset_cost};
     } else {
         VTR_ASSERT(from_rr_type == e_rr_type::SINK);
-        return (0.);
+        return {0., 0.};
     }
 }
 
 /******** Function Definitions ********/
 /* queries the lookahead_map (should have been computed prior to routing) to get the expected cost
  * from the specified source to the specified target */
-std::pair<float, float> MapLookahead::get_expected_delay_and_cong(RRNodeId from_node, RRNodeId to_node, const t_conn_cost_params& params, float /*R_upstream*/) const {
+std::pair<float, float> MapLookahead::get_expected_delay_and_cong(RRNodeId from_node, RRNodeId to_node, const t_conn_cost_params& params, float R_upstream) const {
+    if (is_flat_) {
+        return get_expected_delay_and_cong_flat_router(from_node, to_node, params, R_upstream);
+    }
+    return get_expected_delay_and_cong_global(from_node, to_node, params, R_upstream);
+}
+
+std::pair<float, float> MapLookahead::get_expected_delay_and_cong_global(RRNodeId from_node, RRNodeId to_node, const t_conn_cost_params& params, float /*R_upstream*/) const {
     const auto& device_ctx = g_vpr_ctx.device();
     const auto& rr_graph = device_ctx.rr_graph;
 

vpr/src/route/router_lookahead/router_lookahead_map.h

@@ -16,6 +16,12 @@ class MapLookahead : public RouterLookahead {
 
   private:
     float get_expected_cost_flat_router(RRNodeId current_node, RRNodeId target_node, const t_conn_cost_params& params, float R_upstream) const;
+    //Same as get_expected_cost_flat_router(), but returns the delay and congestion costs separately
+    //instead of their sum (RCV requires this). It is called by get_expected_delay_and_cong() when is_flat_ is true.
+    std::pair<float, float> get_expected_delay_and_cong_flat_router(RRNodeId current_node, RRNodeId target_node, const t_conn_cost_params& params, float R_upstream) const;
+    //The original non-flat routing delay/congestion lookup.
+    //Called directly by get_expected_delay_and_cong_flat_router() and by get_expected_delay_and_cong() when !is_flat_.
+    std::pair<float, float> get_expected_delay_and_cong_global(RRNodeId from_node, RRNodeId to_node, const t_conn_cost_params& params, float R_upstream) const;
     //Look-up table from SOURCE/OPIN to CHANX/CHANY of various types
     util::t_src_opin_delays src_opin_delays;
     // Lookup table from a tile pins to the primitive classes inside that tile

vtr_flow/parse/pass_requirements/pass_requirements_hold_optimization.txt

@@ -0,0 +1,11 @@
+#Pass requirements for the strong_yoyo_flat_router tests.
+#These tests check whether the yoyo routing budgets algorithm can resolve
+#hold violations under flat routing. Only the VPR run status and the final
+#hold slack are checked. All other QoR metrics are not checked in this test.
+
+#Common VPR status metrics
+%include "common/pass_requirements.vpr_status.txt"
+
+#Hold slack should be equal to zero
+hold_TNS;Equal()
+hold_WNS;Equal()

vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_yoyo_flat_router/basic/config/basic.blif

@@ -0,0 +1,18 @@
+# Generated by Yosys 0.55 (git sha1 60f126cd0, g++ 13.3.0-6ubuntu2~24.04.1 -fPIC -O3)
+
+.model clock_uncertainty
+.inputs d_in rstn clk
+.outputs capture
+.names gnd
+.names vcc
+1
+.names unconn
+.latch $auto$rtlil.cc:3203:MuxGate$148 $sdff~1^Q~0 re clk 2
+.latch $auto$rtlil.cc:3203:MuxGate$150 capture re clk 2
+.names gnd d_in rstn $auto$rtlil.cc:3203:MuxGate$148
+1-0 1
+-11 1
+.names gnd $sdff~1^Q~0 rstn $auto$rtlil.cc:3203:MuxGate$150
+1-0 1
+-11 1
+.end

vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_yoyo_flat_router/basic/config/basic.sdc

@@ -0,0 +1,9 @@
+# Clock
+create_clock -period 0 [get_ports clk]
+
+# Apply a 500ps uncertainty to the clock for both setup and hold
+set_clock_uncertainty -to [get_clocks {clk}] 0.5
+
+# Constrain all I/Os
+set_input_delay -clock clk -max 0 [get_ports {*}]
+set_output_delay -clock clk -max 0 [get_ports {*}]

vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_yoyo_flat_router/basic/config/config.txt

@@ -0,0 +1,28 @@
+#
+############################################
+# Configuration file for running experiments
+##############################################
+
+# Path to directory of circuits to use
+circuits_dir=tasks/regression_tests/vtr_reg_strong/strong_yoyo_flat_router/basic/config
+
+# Path to directory of architectures to use
+archs_dir=arch/timing
+
+# Add circuits to list to sweep
+circuit_list_add=basic.blif
+
+# Add architectures to list to sweep
+arch_list_add=k6_frac_N10_frac_chain_mem32K_40nm.xml
+
+# Parse info and how to parse
+parse_file=vpr_fixed_chan_width.txt
+
+# How to parse QoR info
+qor_parse_file=qor_fixed_chan_width.txt
+
+# Pass requirements
+pass_requirements_file=pass_requirements_hold_optimization.txt
+
+script_params_common=-starting_stage vpr --sdc_file tasks/regression_tests/vtr_reg_strong/strong_yoyo_flat_router/basic/config/basic.sdc
+script_params_list_add = --route_chan_width 34 --flat_routing on --routing_budgets_algorithm yoyo

vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_yoyo_flat_router/basic/config/golden_results.txt

@@ -0,0 +1,2 @@
+arch	circuit	script_params	vtr_flow_elapsed_time	vtr_max_mem_stage	vtr_max_mem	error	odin_synth_time	max_odin_mem	parmys_synth_time	max_parmys_mem	abc_depth	abc_synth_time	abc_cec_time	abc_sec_time	max_abc_mem	ace_time	max_ace_mem	num_clb	num_io	num_memories	num_mult	vpr_status	vpr_revision	vpr_build_info	vpr_compiler	vpr_compiled	hostname	rundir	max_vpr_mem	num_primary_inputs	num_primary_outputs	num_pre_packed_nets	num_pre_packed_blocks	num_netlist_clocks	num_post_packed_nets	num_post_packed_blocks	device_width	device_height	device_grid_tiles	device_limiting_resources	device_name	pack_mem	pack_time	initial_placed_wirelength_est	placed_wirelength_est	total_swap	accepted_swap	rejected_swap	aborted_swap	place_mem	place_time	place_quench_time	initial_placed_CPD_est	placed_CPD_est	placed_setup_TNS_est	placed_setup_WNS_est	placed_geomean_nonvirtual_intradomain_critical_path_delay_est	place_delay_matrix_lookup_time	place_quench_timing_analysis_time	place_quench_sta_time	place_total_timing_analysis_time	place_total_sta_time	ap_mem	ap_time	ap_full_legalizer_mem	ap_full_legalizer_time	routed_wirelength	avg_routed_wirelength	routed_wiresegment	avg_routed_wiresegment	total_nets_routed	total_connections_routed	total_heap_pushes	total_heap_pops	logic_block_area_total	logic_block_area_used	routing_area_total	routing_area_per_tile	crit_path_route_success_iteration	num_rr_graph_nodes	num_rr_graph_edges	collapsed_nodes	critical_path_delay	geomean_nonvirtual_intradomain_critical_path_delay	setup_TNS	setup_WNS	hold_TNS	hold_WNS	create_rr_graph_time	create_intra_cluster_rr_graph_time	adding_internal_edges	route_mem	crit_path_route_time	crit_path_total_timing_analysis_time	crit_path_total_sta_time	router_lookahead_mem	tile_lookahead_computation_time	router_lookahead_computation_time	
+k6_frac_N10_frac_chain_mem32K_40nm.xml	basic.blif	common_--route_chan_width_34_--flat_routing_on_--routing_budgets_algorithm_yoyo	0.51	vpr	69.35 MiB		-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	1	3	0	0	success	v8.0.0-17665-g1fd59f8f5e	release IPO VTR_ASSERT_LEVEL=2	GNU 13.3.0 on Linux-6.17.0-19-generic x86_64	2026-08-27T00:50:40	minchan-ThinkPad-T14s-Gen-1	/home/minchan/work/vtr-verilog-to-routing/vtr_flow/tasks	71016	3	1	8	9	1	4	5	3	3	9	-1	auto	27.6 MiB	0.01	9	9	12	7	4	1	65.7 MiB	0.00	0.00	0.603526	0.545	-1.42731	-0.545	0.545	0.00	5.4823e-05	3.8132e-05	0.000345771	0.000265596	65.7 MiB	0.11	65.7 MiB	0.10	28	4.00000	28	4.00000	22	32	2357	503	53894	53894	7883.24	875.916	7	602	4630	65	1.5627	1.5627	-3.25134	-1.5627	0	0	0.00	0.01	0.00	69.4 MiB	0.23	0.00633122	0.004496	25.9 MiB	0.17	0.00	

vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_yoyo_flat_router/matmul/config/config.txt

@@ -0,0 +1,28 @@
+#
+############################################
+# Configuration file for running experiments
+##############################################
+
+# Path to directory of circuits to use
+circuits_dir=tasks/regression_tests/vtr_reg_strong/strong_yoyo_flat_router/matmul/config
+
+# Path to directory of architectures to use
+archs_dir=arch/timing
+
+# Add circuits to list to sweep
+circuit_list_add=matmul.blif
+
+# Add architectures to list to sweep
+arch_list_add=k6_frac_N10_frac_chain_mem32K_40nm.xml
+
+# Parse info and how to parse
+parse_file=vpr_fixed_chan_width.txt
+
+# How to parse QoR info
+qor_parse_file=qor_fixed_chan_width.txt
+
+# Pass requirements
+pass_requirements_file=pass_requirements_hold_optimization.txt
+
+script_params_common=-starting_stage vpr --sdc_file tasks/regression_tests/vtr_reg_strong/strong_yoyo_flat_router/matmul/config/matmul.sdc
+script_params_list_add = --route_chan_width 58 --flat_routing on --routing_budgets_algorithm yoyo

vtr_flow/tasks/regression_tests/vtr_reg_strong/strong_yoyo_flat_router/matmul/config/golden_results.txt

@@ -0,0 +1,2 @@
+arch	circuit	script_params	vtr_flow_elapsed_time	vtr_max_mem_stage	vtr_max_mem	error	odin_synth_time	max_odin_mem	parmys_synth_time	max_parmys_mem	abc_depth	abc_synth_time	abc_cec_time	abc_sec_time	max_abc_mem	ace_time	max_ace_mem	num_clb	num_io	num_memories	num_mult	vpr_status	vpr_revision	vpr_build_info	vpr_compiler	vpr_compiled	hostname	rundir	max_vpr_mem	num_primary_inputs	num_primary_outputs	num_pre_packed_nets	num_pre_packed_blocks	num_netlist_clocks	num_post_packed_nets	num_post_packed_blocks	device_width	device_height	device_grid_tiles	device_limiting_resources	device_name	pack_mem	pack_time	initial_placed_wirelength_est	placed_wirelength_est	total_swap	accepted_swap	rejected_swap	aborted_swap	place_mem	place_time	place_quench_time	initial_placed_CPD_est	placed_CPD_est	placed_setup_TNS_est	placed_setup_WNS_est	placed_geomean_nonvirtual_intradomain_critical_path_delay_est	place_delay_matrix_lookup_time	place_quench_timing_analysis_time	place_quench_sta_time	place_total_timing_analysis_time	place_total_sta_time	ap_mem	ap_time	ap_full_legalizer_mem	ap_full_legalizer_time	routed_wirelength	avg_routed_wirelength	routed_wiresegment	avg_routed_wiresegment	total_nets_routed	total_connections_routed	total_heap_pushes	total_heap_pops	logic_block_area_total	logic_block_area_used	routing_area_total	routing_area_per_tile	crit_path_route_success_iteration	num_rr_graph_nodes	num_rr_graph_edges	collapsed_nodes	critical_path_delay	geomean_nonvirtual_intradomain_critical_path_delay	setup_TNS	setup_WNS	hold_TNS	hold_WNS	create_rr_graph_time	create_intra_cluster_rr_graph_time	adding_internal_edges	route_mem	crit_path_route_time	crit_path_total_timing_analysis_time	crit_path_total_sta_time	router_lookahead_mem	tile_lookahead_computation_time	router_lookahead_computation_time	
+k6_frac_N10_frac_chain_mem32K_40nm.xml	matmul.blif	common_--route_chan_width_58_--flat_routing_on_--routing_budgets_algorithm_yoyo	7.14	vpr	84.60 MiB		-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	35	45	5	1	success	v8.0.0-17665-g1fd59f8f5e	release IPO VTR_ASSERT_LEVEL=2	GNU 13.3.0 on Linux-6.17.0-19-generic x86_64	2026-08-27T00:50:40	minchan-ThinkPad-T14s-Gen-1	/home/minchan/work/vtr-verilog-to-routing/vtr_flow/tasks	86628	45	23	1093	947	1	485	109	20	20	400	memory	auto	45.7 MiB	0.44	3773.98	3307	11549	2515	8548	486	84.6 MiB	0.16	0.00	6.09873	5.76405	-2130.43	-5.76405	5.76405	0.00	0.00167479	0.00145173	0.0892218	0.0781689	84.6 MiB	1.57	84.6 MiB	0.63	6316	5.79450	1690	1.55046	3041	9399	4832591	3078472	2.07112e+07	5.02229e+06	1.47095e+06	3677.38	19	59063	378727	9781	6.31939	6.31939	-2440.64	-6.31939	0	0	0.23	0.53	0.42	84.6 MiB	5.17	0.486731	0.425907	45.7 MiB	0.16	0.08