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Handle non-sink leaves when reloading tracebacks - #3790

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sleepybishop wants to merge 1 commit into
verilog-to-routing:masterfrom
sleepybishop:route-reload
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Handle non-sink leaves when reloading tracebacks#3790
sleepybishop wants to merge 1 commit into
verilog-to-routing:masterfrom
sleepybishop:route-reload

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This PR fixes a bug in traceback reloading. A traceback branch ends when its switch is undefined. Previously, it assumed most branches end at SINK nodes, but non-configurable routing can also leave a non-SINK leaf in the route tree. This is related to the refactoring in #3672.

@github-actions github-actions Bot added VPR VPR FPGA Placement & Routing Tool lang-cpp C/C++ code labels Aug 29, 2026
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sleepybishop marked this pull request as ready for review August 29, 2026 19:34
@AmirhosseinPoolad

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Thanks for the PR!

We would need end to end regression test of a circuit and architecture pair that fails in current master but passes with this change before we can merge this. We explain how this is done here:
https://docs.verilogtorouting.org/en/latest/README.developers/#adding-tests

The unit test is unfortunately not helpful, please remove it.

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