Toy compiler/simulation chain for learning FPGA compilation flow and routing.
Most of the work happened in two bursts:
- January 23, 2026: bootstrapped the compiler/sim pipeline, example designs, and docs.
- January 25-26, 2026: focused heavily on routing and visualizer work (CLB wiring, routing behavior, and drawing/state visualization).
At the time, I was deeply interested in understanding FPGAs, especially how routing works in practice. Building this was a way to force that understanding end-to-end.
Once I felt I had internalized the core routing/model concepts, continuing to develop the simulator started feeling more like chore work than something enlightening.