A couple of small accuracy improvements#48
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The segment registers are always 16-bit. Pushing them onto 32-bit stack
segment advances the stack pointer by 32 bits, but only writes 16 bits,
keeping the most significant 16 bits unchanged.
On an Intel Core i7 (stepping 12):
$ cat pushseg.c
#include <stdio.h>
int
main ()
{
long wrd;
asm (
"push $0x12345678\n\t"
"pop %%eax\n\t"
"push %%ss\n\t"
"pop %0\n\t"
: "=r" (wrd) :
);
printf ("0x%08x\n", wrd);
}
$ cc -m32 pushseg.c
$ ./a.out
0x1234002b
$
Left shift is documented to leave AF undefined, but in reality it resets
the flag if the bit count is different from zero.
On an Intel Core i7 (stepping 12):
$ cat shlaf.c
#include <stdio.h>
int
main ()
{
long wrd;
asm (
"mov $0xffffffff, %%ecx\n\t"
"push $0x210\n\t" // IF | AF
"popf\n\t"
"shl $1, %%ecx\n\t"
"pushf\n\t"
"pop %0\n\t"
: "=r" (wrd) :
);
printf ("AF%c\n", wrd & 0x10 ? '+' : '-');
}
$ cc -m32 shlaf.c
$ ./a.out
AF-
$
wfeldt
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Jul 22, 2025
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Not on my AMD processor, afaics.
While the AMD doc is not specific enough,
"Intel 64 and IA-32 Architectures Software Developer’s Manual" says:
If the source operand is a segment register (16 bits) and the operand size
is 64-bits, a zero- extended value is pushed on the stack; if the operand
size is 32-bits, either a zero-extended value is pushed on the stack or the
segment selector is written on the stack using a 16-bit move. For the last
case, all recent Core and Atom processors perform a 16-bit move, leaving the
upper portion of the stack location unmodified
So it can be either way.
It might make sense to have it configurable.
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While hunting out a suspected bug (which turned out to be a false alarm) while running OpenFirmware x86 Forth dictionaries, I've noticed some differences in libx86emu compared to my actual Intel processor. I've patched them to rule them out as culprits of my bug -- this branch contains the patches + test cases.
I don't think any of these are actually bugs, but it still might be useful for emulation to mimic actual hardware more closely.