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Add asserts to br_cdc_bit_pulse and scrub some obsolete TODOs #653

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Add asserts to br_cdc_bit_pulse and scrub some obsolete TODOs #653

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fa30f87
Scrub some obsolete TODOs
mgottscho Apr 25, 2025
bd52c59
Merge branch 'main' into mgottscho/todo-scrub
mgottscho May 17, 2025
e9bb8e6
Merge branch 'main' into mgottscho/todo-scrub
mgottscho Nov 12, 2025
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Merge branch 'main' into mgottscho/todo-scrub
mgottscho Nov 12, 2025
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2 changes: 0 additions & 2 deletions arb/rtl/br_arb_lru.sv
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Expand Up @@ -66,6 +66,4 @@ module br_arb_lru #(
|-> $stable(grant))
`BR_COVER_IMPL(grant_without_state_update_c, !enable_priority_update && |grant)

// TODO(mgottscho): Add more cases

endmodule : br_arb_lru
3 changes: 0 additions & 3 deletions arb/rtl/br_arb_rr.sv
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Expand Up @@ -74,7 +74,4 @@ module br_arb_rr #(
|-> $stable(grant))
`BR_COVER_IMPL(grant_without_state_update_c, !enable_priority_update && |grant)

// TODO(mgottscho): Add more cases
// TODO(mgottscho): Add covers on masked and unmasked cases

endmodule : br_arb_rr
17 changes: 14 additions & 3 deletions cdc/rtl/br_cdc_bit_pulse.sv
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Expand Up @@ -67,10 +67,18 @@ module br_cdc_bit_pulse #(
input logic dst_rst,
output logic dst_pulse
);
// Integration Assertions

//------------------------------------------
// Integration checks
//------------------------------------------
// Relying on checks in br_cdc_bit_toggle

`BR_ASSERT_CR_INTG(src_pulse_high_then_low_a, src_pulse |=> !src_pulse, src_clk, src_rst)

@zhemao-openai zhemao-openai Apr 25, 2025

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I didn't add these in my PR because I think this is too stringent. If the source clock is much slower than the destination clock, it would be perfectly fine to have two back to back pulses.

@mgottscho mgottscho Apr 28, 2025

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I disagree: the purpose of the module is to transfer pulses. If you're saying you don't have to pulse on the sender side then it seems ill-defined?

Also "two back to back pulses" means there must be a falling edge between, no?

`BR_COVER_CR_INTG(back_to_back_src_pulse_c, src_pulse ##2 src_pulse, src_clk, src_rst)

@zhemao-openai zhemao-openai Apr 25, 2025

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Conversely, if the source clock is much faster than the destination clock, it may not be safe to have pulses two cycles apart on the source clock.

@mgottscho mgottscho Apr 28, 2025

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I suppose if this is true then you should probably use a 1-bit CDC FIFO?

@zhemao-openai zhemao-openai Apr 28, 2025

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If you can guarantee that the pulses are sufficiently spaced on the source side, you don't need to use a FIFO. I think if you want to add this cover, you should have a parameter like MinPulseSeparation.

@mgottscho mgottscho May 3, 2025

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Right so I only see two possibilities. Unless I'm missing something.

  1. If you want to guarantee no data loss - use a CDC FIFO.
  2. If you can guarantee the source pulses are far enough apart that they can be synchronized to destination - use this.

If 2, then shouldn't we have the source side assert MinPulseSeparation unconditionally? If it fails, the user should switch to CDC FIFO for their use case?

@zhemao-openai zhemao-openai May 7, 2025

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Yes, I think have an assert that the pulses are minimum number of cycles apart and have the minimum be configurable.


//------------------------------------------
// Implementation
//------------------------------------------
logic src_level;
logic dst_level;
logic dst_level_d;
Expand Down Expand Up @@ -109,7 +117,10 @@ module br_cdc_bit_pulse #(
assign dst_pulse = dst_pulse_internal;
end

// Implementation assertions
// TODO(zhemao): Add some here
//------------------------------------------
// Implementation checks
//------------------------------------------
`BR_ASSERT_CR_IMPL(dst_pulse_high_then_low_a, dst_pulse |=> !dst_pulse, dst_clk, dst_rst)
`BR_COVER_CR_IMPL(back_to_back_dst_pulse_c, dst_pulse ##2 dst_pulse, dst_clk, dst_rst)

endmodule
2 changes: 0 additions & 2 deletions enc/rtl/br_enc_bin2onehot.sv
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Expand Up @@ -41,8 +41,6 @@
// It must be at least $clog2(NumValues) but may be set larger than the minimum
// width. Irrespective of the width, the input binary must be in the allowed range
// 0 <= in < NumValues.
//
// TODO(mgottscho): Write spec

`include "br_asserts_internal.svh"

Expand Down
3 changes: 0 additions & 3 deletions enc/sim/br_enc_bin2onehot_tb.sv
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Expand Up @@ -92,9 +92,6 @@ module br_enc_bin2onehot_tb;
// Finish simulation
#10;

// TODO(mgottscho): not enough information to know if test passed.
// If DUT asserts fire, we can't see that here.
// Need to determine pass/fail outside of this TB?
if (errors) begin
$display("Number of errors: %0d", errors);
$display("TEST FAILED");
Expand Down
2 changes: 0 additions & 2 deletions flow/rtl/br_flow_arb_fixed.sv
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Expand Up @@ -22,8 +22,6 @@
// Purely combinational (no delays).
// Pop valid can be unstable if push valid is unstable and all active push_valid
// are withdrawn while pop_ready is low.
//
// TODO(mgottscho): Write spec

`include "br_asserts_internal.svh"

Expand Down
4 changes: 0 additions & 4 deletions flow/rtl/br_flow_arb_lru.sv
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Expand Up @@ -23,8 +23,6 @@
// the internal arbiter priority state.
// Pop valid can be unstable if push valid is unstable and all active push_valid
// are withdrawn while pop_ready is low.
//
// TODO(mgottscho): Write spec

`include "br_registers.svh"
`include "br_asserts_internal.svh"
Expand Down Expand Up @@ -56,8 +54,6 @@ module br_flow_arb_lru #(
//------------------------------------------
// Rely on submodule integration checks

// TODO(mgottscho): Add more

//------------------------------------------
// Implementation
//------------------------------------------
Expand Down
4 changes: 0 additions & 4 deletions flow/rtl/br_flow_arb_rr.sv
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Expand Up @@ -23,8 +23,6 @@
// the internal arbiter priority state.
// Pop valid can be unstable if push valid is unstable and all active push_valid
// are withdrawn while pop_ready is low.
//
// TODO(mgottscho): Write spec

`include "br_registers.svh"
`include "br_asserts_internal.svh"
Expand Down Expand Up @@ -56,8 +54,6 @@ module br_flow_arb_rr #(
//------------------------------------------
// Rely on submodule integration checks

// TODO(mgottscho): Add more

//------------------------------------------
// Implementation
//------------------------------------------
Expand Down
2 changes: 0 additions & 2 deletions flow/rtl/br_flow_demux_select.sv
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Expand Up @@ -22,8 +22,6 @@
// Data progresses from one stage to another when both
// the corresponding ready signal and valid signal are
// both 1 on the same cycle. Otherwise, the stage is stalled.
//
// TODO(mgottscho): Write spec doc

`include "br_registers.svh"

Expand Down
2 changes: 0 additions & 2 deletions flow/rtl/br_flow_demux_select_unstable.sv
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Expand Up @@ -28,8 +28,6 @@
// It is called "unstable" because the pop interface is not guaranteed
// to follow the ready-valid stability convention, because the select
// input could change while the selected pop interface is backpressuring.
//
// TODO(mgottscho): Write spec doc

`include "br_asserts_internal.svh"

Expand Down
2 changes: 0 additions & 2 deletions flow/rtl/br_flow_mux_select.sv
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Expand Up @@ -22,8 +22,6 @@
// Data progresses from one stage to another when both
// the corresponding ready signal and valid signal are
// both 1 on the same cycle. Otherwise, the stage is stalled.
//
// TODO(mgottscho): Write spec doc

`include "br_registers.svh"

Expand Down
2 changes: 0 additions & 2 deletions flow/rtl/br_flow_mux_select_unstable.sv
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Expand Up @@ -28,8 +28,6 @@
// It is called "unstable" because the pop interface is not guaranteed
// to follow the ready-valid stability convention, because the select
// input could change while the selected push interface is backpressured.
//
// TODO(mgottscho): Write spec doc

`include "br_asserts_internal.svh"

Expand Down