Merge pull request #96 from carlosqwqqwq/riscv-abpoa

Add explicit RISC-V portable build support

Author: yangao07

CMakeLists.txt

@@ -23,6 +23,8 @@ elseif(CMAKE_SYSTEM_PROCESSOR MATCHES "^(aarch64|arm64|ARM64)$")
     set(_ABPOA_AARCH64 TRUE)
 elseif(CMAKE_SYSTEM_PROCESSOR MATCHES "^armv7")
     set(_ABPOA_ARM32 TRUE)
+elseif(CMAKE_SYSTEM_PROCESSOR MATCHES "^(riscv64|riscv32|riscv)")
+    set(_ABPOA_RISCV TRUE)
 endif()
 
 if(_ABPOA_X86_64)
@@ -169,6 +171,15 @@ elseif(_ABPOA_WASM)
     target_sources(abpoa PRIVATE src/abpoa_align_simd.c)
     target_compile_options(abpoa PRIVATE -msimd128)
 
+elseif(_ABPOA_RISCV)
+    # RISC-V: like ARM, use the existing SIMDE-backed AVX2-flavored path
+    # without injecting host-specific march flags or x86 dispatch machinery.
+    # Leaving __AVX2__ undefined falls back to the 128-bit SSE2-style path,
+    # which is not the project's validated portable configuration.
+    message(STATUS "RISC-V target detected; building abPOA with the portable SIMDE path")
+    target_sources(abpoa PRIVATE src/abpoa_align_simd.c)
+    target_compile_definitions(abpoa PRIVATE __AVX2__)
+
 else()
     # Fallback: single compile with -march=native
     target_sources(abpoa PRIVATE src/abpoa_align_simd.c)

Makefile

@@ -72,6 +72,11 @@ else
 endif
 endif
 
+ifneq ($(filter riscv%,$(ARCH)),)
+	SIMD_FLAG = -D__AVX2__
+	OBJS = ${BASIC_OBJS} $(addprefix $(SRC_DIR)/, abpoa_align_simd.o)
+endif
+
 # override if user specified
 ifneq ($(armv7),) # for ARMv7
 	SIMD_FLAG   =  -march=armv7-a -mfpu=neon -D__AVX2__

README.md

@@ -79,6 +79,9 @@ significant speed improvement over existing tools.
 
 abPOA supports three alignment modes (global, local, extension) and flexible scoring schemes that allow linear, affine and convex gap penalties. 
 It right now supports SSE2/SSE4.1/AVX2 vectorization.
+For `riscv64`, the current portability path uses the existing SIMDE-backed
+AVX2-style generic build rather than x86 runtime dispatch or a dedicated RVV
+backend.
 
 For more information, please refer to our [paper](https://dx.doi.org/10.1093/bioinformatics/btaa963) published in Bioinformatics.
 

setup.py

@@ -26,6 +26,8 @@
         simd_flag = ['-march=armv8-a+simd', '-D__AVX2__']
     elif machine_arch in ["aarch32"]:
         simd_flag = ['-march=armv8-a+simd', '-mfpu=auto -D__AVX2__']
+    elif machine_arch.startswith("riscv"):
+        simd_flag = ['-D__AVX2__']
     else: # x86_64
         simd_flag=['-march=native']
         if os.getenv('SSE4', False):