boards: gd: gd32f470z_start: add initial support

boards/gd/gd32f470z_start/Kconfig.gd32f470z_start

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+# Copyright (c) 2026 Zhijian Han
+# SPDX-License-Identifier: Apache-2.0
+
+config BOARD_GD32F470Z_START
+	select SOC_GD32F470

boards/gd/gd32f470z_start/board.cmake

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+# Copyright (c) 2026 Zhijian Han
+# SPDX-License-Identifier: Apache-2.0
+
+# GD32F470xx series is not yet in the SEGGER J-Link device database.
+# Use the closest GD32F450 device as a stand-in (same Cortex-M4F core,
+# flash base 0x08000000, SRAM base 0x20000000 and identical CPU TAP ID).
+board_runner_args(jlink "--device=GD32F450ZK" "--speed=4000")
+
+# Make J-Link the default runner, since it is the most common probe used with
+# this board. OpenOCD (CMSIS-DAP) remains available via --runner openocd.
+include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake)
+include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake)

boards/gd/gd32f470z_start/board.yml

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+board:
+  name: gd32f470z_start
+  full_name: GD32F470Z-START
+  vendor: gd
+  socs:
+    - name: gd32f470

boards/gd/gd32f470z_start/doc/index.rst

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+.. zephyr:board:: gd32f470z_start
+
+Overview
+********
+
+The GD32F470Z-START board is a minimal system board based on the
+GigaDevice GD32F470ZIT6 Cortex-M4F MCU. It is produced by Huqin Zhiyuan
+(慧勤智远) as the "GD32F470ZIT6 Core Board V1.1".
+
+The GD32F470ZIT6 features a single-core ARM Cortex-M4F MCU which can run
+up to 240 MHz with flash accesses at zero wait states, 2048 KiB of Flash
+and 768 KiB of SRAM.
+
+Hardware
+********
+
+- GD32F470ZIT6 MCU (LQFP144, 240 MHz)
+- 2 x user LEDs (LED1 red on PA1, LED2 green on PA2, active-low)
+- 2 x user push buttons (KEY0 on PC1, WK_UP on PA0, active-high)
+- 1 x reset button
+- USB-C to UART (CH340X) on USART0 (TX PA9 / RX PA10)
+- AT24C02 EEPROM (256 B) on I2C0 (SCL PB6 / SDA PB7)
+- W25Q128 SPI NOR Flash (16 MB) on SPI4 (CS PF6, SCK PF7, MISO PF8, MOSI PF9)
+- 32 MB SDRAM (W9825G6KH-6I)
+- TF card slot (SDIO)
+- RGB / 8080 / SPI LCD interfaces
+- SWD debug interface
+
+.. figure:: img/gd32f470z_start_alt.webp
+   :align: center
+   :alt: GD32F470Z-START board
+
+   GD32F470Z-START board
+
+Supported Features
+==================
+
+.. zephyr:board-supported-hw::
+
+Programming and Debugging
+*************************
+
+.. zephyr:board-supported-runners::
+
+The board can be programmed and debugged through its SWD interface
+(SWDIO on PA13, SWCLK on PA14). It does not include an onboard debug
+probe, so an external probe (e.g. SEGGER J-Link or CMSIS-DAP) is required.
+
+References
+**********
+
+- `GigaDevice GD32F470 series product page`_
+- `GD32F470xx Datasheet`_
+- `GD32F4xx User Manual`_
+- `GD32F470ZIT6 Core Board V1.1 (vendor store)`_
+
+.. _GigaDevice GD32F470 series product page:
+   https://www.gigadevice.com/product/mcu/high-performance-mcus/gd32f4xx-series/gd32f470
+
+.. _GD32F470xx Datasheet:
+   https://gd32mcu.com/data/documents/datasheet/GD32F470xx_Datasheet_Rev1.3.pdf
+
+.. _GD32F4xx User Manual:
+   https://gd32mcu.com/data/documents/userManual/GD32F4xx_User_Manual_Rev2.7.pdf
+
+.. _GD32F470ZIT6 Core Board V1.1 (vendor store):
+   https://e.tb.cn/h.89TFpCnFP1XKlE2?tk=dVyITWM5Ejs

boards/gd/gd32f470z_start/gd32f470z_start-pinctrl.dtsi

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+/*
+ * Copyright (c) 2026 Zhijian Han
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <dt-bindings/pinctrl/gd32f470z(e-g-i-k)xx-pinctrl.h>
+
+&pinctrl {
+	usart0_default: usart0_default {
+		group1 {
+			pinmux = <USART0_TX_PA9>, <USART0_RX_PA10>;
+		};
+	};
+
+	i2c0_default: i2c0_default {
+		group1 {
+			pinmux = <I2C0_SCL_PB6>, <I2C0_SDA_PB7>;
+			drive-open-drain;
+		};
+	};
+
+	spi4_default: spi4_default {
+		group1 {
+			pinmux = <SPI4_SCK_PF7>, <SPI4_MISO_PF8>, <SPI4_MOSI_PF9>;
+		};
+	};
+};

boards/gd/gd32f470z_start/gd32f470z_start.dts

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+/*
+ * Copyright (c) 2026 Zhijian Han
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/dts-v1/;
+
+#include <gd/gd32f4xx/gd32f470xi.dtsi>
+#include "gd32f470z_start-pinctrl.dtsi"
+#include <zephyr/dt-bindings/input/input-event-codes.h>
+
+/ {
+	model = "GigaDevice GD32F470Z-START";
+	compatible = "gd,gd32f470z-start";
+
+	chosen {
+		zephyr,sram = &sram0;
+		zephyr,flash = &flash0;
+		zephyr,dtcm = &tcmsram0;
+		zephyr,console = &usart0;
+		zephyr,shell-uart = &usart0;
+	};
+
+	leds {
+		compatible = "gpio-leds";
+
+		led1: led1 {
+			gpios = <&gpioa 1 GPIO_ACTIVE_LOW>;
+			label = "LED1";
+		};
+
+		led2: led2 {
+			gpios = <&gpioa 2 GPIO_ACTIVE_LOW>;
+			label = "LED2";
+		};
+	};
+
+	gpio_keys {
+		compatible = "gpio-keys";
+
+		key0: key0 {
+			label = "KEY0";
+			gpios = <&gpioc 1 GPIO_ACTIVE_HIGH>;
+			zephyr,code = <INPUT_KEY_0>;
+		};
+
+		wk_up: wk_up {
+			label = "WK_UP";
+			gpios = <&gpioa 0 GPIO_ACTIVE_HIGH>;
+			zephyr,code = <INPUT_KEY_1>;
+		};
+	};
+
+	aliases {
+		led0 = &led1;
+		led1 = &led2;
+		sw0 = &key0;
+		sw1 = &wk_up;
+		eeprom-0 = &eeprom0;
+	};
+};
+
+&gpioa {
+	status = "okay";
+};
+
+&gpiob {
+	status = "okay";
+};
+
+&gpioc {
+	status = "okay";
+};
+
+&gpiof {
+	status = "okay";
+};
+
+&usart0 {
+	status = "okay";
+	current-speed = <115200>;
+	pinctrl-0 = <&usart0_default>;
+	pinctrl-names = "default";
+};
+
+&i2c0 {
+	status = "okay";
+	pinctrl-0 = <&i2c0_default>;
+	pinctrl-names = "default";
+
+	eeprom0: eeprom@50 {
+		compatible = "atmel,at24";
+		reg = <0x50>;
+		status = "okay";
+		size = <256>;
+		pagesize = <8>;
+		address-width = <8>;
+		timeout = <5>;
+	};
+};
+
+&spi4 {
+	status = "okay";
+	pinctrl-0 = <&spi4_default>;
+	pinctrl-names = "default";
+	cs-gpios = <&gpiof 6 GPIO_ACTIVE_LOW>;
+
+	nor_flash: w25q128@0 {
+		compatible = "jedec,spi-nor";
+		reg = <0>;
+		spi-max-frequency = <80000000>;
+		size = <DT_SIZE_M(16)>;
+		jedec-id = [ef 40 18];
+		status = "okay";
+	};
+};

boards/gd/gd32f470z_start/gd32f470z_start.yaml

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+# Copyright (c) 2026 Zhijian Han
+# SPDX-License-Identifier: Apache-2.0
+
+identifier: gd32f470z_start
+name: GigaDevice GD32F470Z-START
+type: mcu
+arch: arm
+ram: 704
+flash: 2048
+toolchain:
+  - zephyr
+  - gnuarmemb
+supported:
+  - gpio
+  - i2c
+  - spi
+  - uart
+vendor: gd

boards/gd/gd32f470z_start/gd32f470z_start_defconfig

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+# Copyright (c) 2026 Zhijian Han
+# SPDX-License-Identifier: Apache-2.0
+
+CONFIG_ARM_MPU=y
+CONFIG_HW_STACK_PROTECTION=y
+
+CONFIG_CONSOLE=y
+CONFIG_UART_CONSOLE=y
+CONFIG_SERIAL=y
+
+CONFIG_GPIO=y

boards/gd/gd32f470z_start/support/openocd.cfg

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+# Copyright (c) 2026 Zhijian Han
+# SPDX-License-Identifier: Apache-2.0
+
+# GD32F470ZIT6 shares the Cortex-M4F core, flash and SRAM layout with the
+# STM32F4xx family, so reuse its target script. The CPU TAP ID is identical
+# across GD32F4xx devices.
+source [find interface/cmsis-dap.cfg]
+transport select swd
+
+set CHIPNAME gd32f470zk
+set CPUTAPID 0x790007a3
+
+source [find target/stm32f4x.cfg]
+
+reset_config trst_and_srst separate
+
+$_TARGETNAME configure -event gdb-attach {
+	echo "Debugger attaching: halting execution"
+	reset halt
+	gdb_breakpoint_override hard
+}
+
+$_TARGETNAME configure -event gdb-detach {
+	echo "Debugger detaching: resuming execution"
+	resume
+}