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drivers: ethernet: nxp_enet_qos: arm RX timestamping after MAC start - #117411

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drivers: ethernet: nxp_enet_qos: arm RX timestamping after MAC start#117411
bperseghetti wants to merge 1 commit into
zephyrproject-rtos:mainfrom
CogniPilot:pr-deps-enet-qos-gptp-timestamp

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@bperseghetti

@bperseghetti bperseghetti commented Aug 26, 2026

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The PTP clock driver programs MAC_TIMESTAMP_CONTROL at its own init time, which can run before enet_qos_start() enables the receiver. On cold boots with that ordering the RX timestamp snapshot logic never arms: and received PTP frames carry no hardware timestamps, so gPTP path delay measurement cannot complete and the port never becomes AS capable.

Read back and rewrite MAC_TIMESTAMP_CONTROL after the MAC receiver is enabled. Rewriting the existing value while RX is running is what latches the snapshot configuration, so this is deliberately not a no-op even though it writes back the same register value.

Validated on NXP MCXN947 hardware across repeated cold boots including power-on resets, path delay measurement completes and the port reports AS capable on every boot, where the broken ordering left it permanently incapable.

The receive timestamp snapshot logic on this MAC only arms when
MAC_TIMESTAMP_CONTROL is written while the receiver is enabled. The PTP
clock driver programs that register from its own init routine, and
PTP_CLOCK_INIT_PRIORITY defaults to ETH_INIT_PRIORITY, so the PTP clock
device can initialize before the MAC driver enables the receiver. When
that ordering occurs the configuration is retained in the register but
received frames are never timestamped: the receive descriptor status
stays clear and the DMA writes no timestamp context descriptor, so gPTP
never computes neighborPropDelay and never becomes asCapable.

Rewrite MAC_TIMESTAMP_CONTROL with its existing value once the
transmitter and receiver are running so the snapshot logic latches the
configuration. The register is read back and written unchanged, so this
does not alter the timestamp bit selection and is safe on every ENET
QoS instantiation regardless of init order.

This is independent of the receive-path context descriptor wait already
present in the driver, which covers the separate race where the receive
interrupt arrives before the DMA finishes the descriptor writebacks.
That wait cannot help when the snapshot engine was never armed, because
no timestamp context descriptor is produced at all.

Observed on MCXN947 hardware: rewriting the identical register value
with the MAC running immediately restores receive timestamps.

Signed-off-by: Benjamin Perseghetti <bperseghetti@rudislabs.com>
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