DCache: Add __dcacheline_aligned & __dcacheline_exclusive attributes - #98578
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Setting symbol default value without 'configdefault', or without explicit 'if' checks of dependencies, results in dependency weakening. In this case, CACHE_MANAGEMENT is redefined and set to the given default value even if dependencies D/ICACHE are not enabled. Signed-off-by: Abderrahmane JARMOUNI <git@jarmouni.me> (cherry picked from commit f259c8e)
A component should not rely on the API it is implementing. In this case, the arch layer is implementing the arch cache API (include/zephyr/arch/cache.h), that is used by the public sys cache API (include/zephyr/cache.h), so it can't call the latter. Signed-off-by: Abderrahmane JARMOUNI <git@jarmouni.me> (cherry picked from commit daacc41)
Across the tree, I/DCACHE_LINE_SIZE is required at compile-time for macros, compiler attributes, & linker scripts to function correctly even if run-time cache line detection is available. So remove the dependency of ICACHE_LINE_SIZE on ICACHE_LINE_SIZE_DETECT=n, and of DCACHE_LINE_SIZE on DCACHE_LINE_SIZE_DETECT=n. DCACHE_LINE_SIZE_DETECT & ICACHE_LINE_SIZE_DETECT Kconfig options enable querying some SoC register for finding the i/d-cache line size at the expense of taking more memory and code and a slightly increased boot time. Add new hidden options D/ICACHE_LINE_SIZE_DETECT_SUPPORT only selected by the software component (arch/SoC layer, driver) implementing the system cache API. Signed-off-by: Abderrahmane JARMOUNI <git@jarmouni.me> (cherry picked from commit 7e7c083)
Limit I/DCache line size options' value to [2, UINT32_MAX] at Kconfig level instead of having to check the value in code needlessly. Signed-off-by: Abderrahmane JARMOUNI <git@jarmouni.me> (cherry picked from commit 89aa692)
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When cache is enabled, cache line size should not be zero under any circumstances. The returned value is often used to check address alignment with 'addr & (size -1)', which obviously cannot work if size value is 0. Add asserts to catch invalid values. Signed-off-by: Abderrahmane JARMOUNI <git@jarmouni.me> (cherry picked from commit 48f48a6)
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Add __dcacheline_aligned which ensures data cache line alignment. Add __dcacheline_exclusive_... attributes which puts a static variable in a section that contains only data cache line aligned variables. This results in variables being aligned and having exclusive data cache line(s). Co-authored-by: Krzysztof Chruściński <krzysztof.chruscinski@nordicsemi.no> Signed-off-by: Krzysztof Chruściński <krzysztof.chruscinski@nordicsemi.no> Signed-off-by: Abderrahmane JARMOUNI <git@jarmouni.me>
Replace __aligned(CONFIG_DCACHE_LINE_SIZE) with __dcacheline_aligned across Zephyr Signed-off-by: Abderrahmane JARMOUNI <git@jarmouni.me>
Add tests which checks that variable tagged with __dcacheline_aligned is correctly aligned, and that the variables tagged with __dcacheline_exclusive are in the proper section that gives exclusive data cache line(s) for each. Co-authored-by: Krzysztof Chruściński <krzysztof.chruscinski@nordicsemi.no> Signed-off-by: Krzysztof Chruściński <krzysztof.chruscinski@nordicsemi.no> Signed-off-by: Abderrahmane JARMOUNI <git@jarmouni.me>
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Add test scenario to run cache testcases with linker generator to cover __dcacheline_exclusive_noinit/data attributes CMake code. Signed-off-by: Abderrahmane JARMOUNI <git@jarmouni.me>
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New version of #95888
Add
__dcacheline_alignedattribute which ensures data cache line alignment for variables.Add
__dcacheline_exclusive_noinit&__dcacheline_exclusive_dataattributes which make variables aligned to data cache line size and having exclusive data cache line(s).Usage:
static uint8_t var1 __dcacheline_aligned;static uint8_t var2 __dcacheline_exclusive_noinit;__dcacheline_exclusive_data static uint8_t var3 = 5;