Releases: Logic-Design-Services/CTU-CAN-FD
Releases · Logic-Design-Services/CTU-CAN-FD
v2.7
- RTL: Optimized to remove dead-code and unreachable code
- RTL: Fix frame filters to always pass the Error frame through when IVLD=0.
- RTL: Extend TRV_DELAY to max 256 instead of 128, Extend max SSP position to 512 cycles. Allow up-to 7 bits "in-flight".
- TB: Refactored feature tests -> Massive renaming of feature test functions.
- TB: Split the regression targets into "per-device-config" run -> Small, Medium, Big DUT configs are used.
- TB: Swap to NVC simulator in regression -> Measure code coverage in CI run, reach 100 %
- DOC: Minor fixes based on feedback from community
v2.6
- Implement MODE[ERF] - Error frame logging in RX Buffer
- Implement MODE[SAM] - Self-acknowledge mode
- Implement FRAME_FORMAT_W[LBTBI] - Track index of TXT Buffer used to record Loopback frame.
- Implement FRAME_FORMAT_W[IVLD] - Track if Error frame in RX Buffer does have a valid identifier.
- Fix STATUS[TXPE] and STATUS[TXDPE] not being resetable by Soft-Reset.
- Fix RX Buffer pointer consistency issue if a bit error ocurred in last DLC bit and unit operated in Loop-back mode.
- Fix ignoring of bit error when using SSP, and bit error is sampled in last CRC bit, but not recognized during CRC delimiter.
v2.5
- Added parity protection on RX Buffers and TXT Buffers configurable by
sup_paritygeneric. - Added TXT Buffer Backup mode.
- Debugged all compliance test suites with min/typ/max bit timing configuration
- Rewrote the simulation flow to support VCS simulation with Tropic Square flow as well as Vunit simulation with GHDL.
- Added support for VCS simulator in ISO Compliance library.
- Coverage analysis was done on this release. 99 % overall coverage score was reached. See results at: https://github.com/Blebowski/ctu-can-fd-verification-progress