feat(arm): add ARM architecture support with context and trap handling - #16
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equation314
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luodeb
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Please also add arm target to CI.
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Pull request overview
Adds initial ARM32 (target_arch = "arm") support to the crate by introducing architecture-specific context structures, CPU init/MMU helpers, and bare-metal trap/exception handling (Rust + vector table assembly).
Changes:
- Wire up
armas a supported architecture insrc/lib.rs. - Add
src/arm/*implementing ARM32 context switching, low-level asm wrappers, MMU/trap init, and exception handlers. - Add an ARM-only dependency on
aarch32-cpu(and lockfile updates).
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Copilot reviewed 8 out of 9 changed files in this pull request and generated 7 comments.
Show a summary per file
| File | Description |
|---|---|
| src/lib.rs | Selects arm module when compiling for target_arch = "arm". |
| src/arm/mod.rs | Declares ARM32 submodules and re-exports key types/APIs. |
| src/arm/context.rs | Defines ARM32 TrapFrame, TaskContext, and optional FP state handling. |
| src/arm/asm.rs | Provides ARM32 assembly wrappers (MMU regs, barriers, IRQ control, caches, timers). |
| src/arm/init.rs | Adds ARM32 MMU initialization and trap initialization (vector base + TTBR0). |
| src/arm/trap.rs | Implements Rust-side exception decoding and trap dispatch to handle_trap!. |
| src/arm/trap.S | Adds ARM32 vector table and exception entry/return sequences. |
| Cargo.toml | Adds aarch32-cpu as an ARM-only dependency. |
| Cargo.lock | Locks transitive dependencies introduced by aarch32-cpu. |
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equation314
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Pull request overview
Copilot reviewed 9 out of 10 changed files in this pull request and generated 5 comments.
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equation314
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Please rebase to the latest main branch.
equation314
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Mar 4, 2026
… register management
Replaces inline assembly calls for ARM operations with functions and register accessors from the aarch32-cpu crate, improving safety, readability, and maintainability. Adds aarch32-cpu as a conditional dependency for ARM targets. Modernizes MMU init logic and documents register access for clarity.
Replaces raw inline assembly and custom barriers/TLB invalidation with type-safe abstractions from the CPU crate. Improves readability, correctness, and maintainability by relying on well-tested interfaces for synchronization and control register modification.
Co-authored-by: Copilot <175728472+Copilot@users.noreply.github.com>
equation314
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Mar 9, 2026
…n to proceed to the next instruction when encountering a breakpoint.
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