Skip to content

feat(arm): add ARM architecture support with context and trap handling #16

New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Merged
equation314 merged 27 commits into from
Mar 22, 2026
Merged

feat(arm): add ARM architecture support with context and trap handling #16

Show file tree
Hide file tree
Changes from 25 commits
Commits
Show all changes
27 commits
Select commit Hold shift + click to select a range
80ba1fb
feat(arm): add ARM architecture support with context and trap handling
luodeb Dec 6, 2025
fa8d8e4
feat(arm): enhance exception handling with detailed trap routines and…
luodeb Dec 19, 2025
e4a5797
Refactors ARM assembly usage to leverage aarch32-cpu crate
luodeb Dec 25, 2025
775b32c
Refactors MMU init to use type-safe CPU abstractions
luodeb Dec 25, 2025
3589846
feat(arm): enhance exception handling with new macros and improved re…
luodeb Jan 17, 2026
e46bfbe
refactor(arm): code fmt
luodeb Jan 20, 2026
19ab92a
refactor(arm): streamline assembly function calls and remove unused m…
luodeb Feb 28, 2026
f653dca
Adds ARM timer register access functions
luodeb Feb 28, 2026
5abff1e
improves ARM utilities
luodeb Mar 2, 2026
11a886b
Simplifies ARM MMU setup and improves trap context handling
luodeb Mar 2, 2026
7541c9b
Updates aarch32-cpu dependency version
luodeb Mar 2, 2026
b50022e
Adds support for physical and virtual ARM timers
luodeb Mar 2, 2026
c19e826
Refactors ARM mode and CPSR handling for clarity
luodeb Mar 2, 2026
deb4121
Update src/arm/init.rs
luodeb Mar 2, 2026
580b7a1
No code changes detected
luodeb Mar 2, 2026
a081035
Fix program crashes caused by accidental loss of the`lr` register
luodeb Mar 4, 2026
993c7ae
add ci and rename SAVE_REGS_SVC
luodeb Mar 5, 2026
22e7b83
Simplifies trap frame register restoration logic
luodeb Mar 9, 2026
cfa91db
Clears trap frame lr to detect invalid returns
luodeb Mar 9, 2026
6ec4ecb
Preserves SVC lr in trap frame for correct returns
luodeb Mar 10, 2026
f795db0
Handling debug events in prefetch abort exceptions, allowing executio…
luodeb Mar 16, 2026
24bd5d9
add read/write_thread_pointer
luodeb Mar 16, 2026
71df8f1
Adds ARM32 TLS accessor for Rust compiler support
luodeb Mar 16, 2026
da5fc17
add uspace for arceos clippy
luodeb Mar 16, 2026
cc699a9
code fmt
luodeb Mar 17, 2026
7763792
Switches thread pointer ops to use read-only register
luodeb Mar 20, 2026
159a869
update percpu to 0.3
luodeb Mar 20, 2026
File filter

Filter by extension

Filter by extension
Conversations
Failed to load comments.
Loading
Jump to
Jump to file
Failed to load files.
Loading
Diff view
Diff view
1 change: 1 addition & 0 deletions .github/workflows/check.yml
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -19,6 +19,7 @@ jobs:
- x86_64-unknown-none
- riscv64gc-unknown-none-elf
- aarch64-unknown-none-softfloat
- armv7a-none-eabi
- loongarch64-unknown-none-softfloat

steps:
Expand Down
85 changes: 85 additions & 0 deletions Cargo.lock
View file
Open in desktop

Some generated files are not rendered by default. Learn more about how customized files appear on GitHub.

3 changes: 3 additions & 0 deletions Cargo.toml
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -46,6 +46,9 @@ lazyinit = "0.2"
aarch64-cpu = "11.2"
tock-registers = "0.10"

[target.'cfg(target_arch = "arm")'.dependencies]
aarch32-cpu = "0.2.0"
Comment thread
luodeb marked this conversation as resolved.

[target.'cfg(any(target_arch = "riscv32", target_arch = "riscv64"))'.dependencies]
riscv = "0.16"

Expand Down
Loading
Loading