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Pull requests: cornell-zhang/allo
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fix: fp16 (half) type support in Vitis HLS backend
#579
opened Apr 14, 2026 by
sunwookim028
Contributor
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fix: hierarchical dataflow simulator deadlock and HLS codegen (#561, #565)
#577
opened Apr 13, 2026 by
sunwookim028
Contributor
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[Frontend][IR][LLVM] Add end-to-end QDQ lowering with roundeven + clamp
#575
opened Mar 19, 2026 by
jb2733
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4 tasks done
[Fix] Sort dataflow kernel calls so producers precede consumers
#574
opened Mar 17, 2026 by
zzzDavid
Contributor
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4 tasks done
[Frontend][IR] (1/N) Preparation for new IR builder
#570
opened Mar 15, 2026 by
Fangtangtang
Collaborator
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3 of 4 tasks
[Frontend] Introduce proxy-based schedule frontend backed by Transform Dialect
#569
opened Mar 15, 2026 by
kkkaishao
Contributor
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3 of 4 tasks
[Python] Introduce custom lightweight Python bindings with semantic builder APIs
#568
opened Mar 15, 2026 by
kkkaishao
Contributor
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2 of 4 tasks
[IR] Improve Allo TransformOps implementation and add MLIR tooling
#567
opened Mar 15, 2026 by
kkkaishao
Contributor
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3 of 4 tasks
[Example] add flashattention in example and modify ci test
#564
opened Mar 6, 2026 by
RuizeYu05
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4 tasks
fix: strip MLIR %alloc names from VHLS csim output and handle ap_int in nanobind wrapper
#554
opened Feb 26, 2026 by
sunwookim028
Contributor
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[Backend][HLS] AST for XLS DSLX Backend
#525
opened Jan 18, 2026 by
AnthonyBSong
Contributor
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4 tasks
[Example] Accelerating Sparse MoE Layer on FPGA using Allo
#489
opened Dec 13, 2025 by
zhangxiaohuang1111
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4 tasks
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