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Allo AIE Test Allo AIE Test #19: Scheduled
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Allo FPGA Weekly Test Allo FPGA Weekly Test #13: Scheduled
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fix: fp16 (half) type support in Vitis HLS backend Allo Test #1163: Pull request #579 synchronize by sunwookim028
6m 16s sunwookim028:fix/fp16-hls-half-type
sunwookim028:fix/fp16-hls-half-type
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fix: fp16 (half) type support in Vitis HLS backend Allo Test #1162: Pull request #579 opened by sunwookim028
1m 9s sunwookim028:fix/fp16-hls-half-type
sunwookim028:fix/fp16-hls-half-type
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fix: add float16->half type mapping for Vitis HLS backend Allo Test #1161: Pull request #578 synchronize by sunwookim028
1m 10s sunwookim028:feature/mesh-accelerator
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fix: add float16->half type mapping for Vitis HLS backend Build documentation #302: Pull request #578 synchronize by sunwookim028
2m 43s sunwookim028:feature/mesh-accelerator
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fix: add float16->half type mapping for Vitis HLS backend Allo Test #1160: Pull request #578 synchronize by sunwookim028
4m 35s sunwookim028:feature/mesh-accelerator
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fix: add float16->half type mapping for Vitis HLS backend Build documentation #301: Pull request #578 synchronize by sunwookim028
3m 27s sunwookim028:feature/mesh-accelerator
sunwookim028:feature/mesh-accelerator
3m 27s
fix: strip MLIR %alloc names from VHLS csim output and handle ap_int in nanobind wrapper Allo Test #1159: Pull request #554 synchronize by sunwookim028
6m 0s sunwookim028:fix/vhls-mlir-percent-alloc-csim
sunwookim028:fix/vhls-mlir-percent-alloc-csim
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fix: add float16->half type mapping for Vitis HLS backend Build documentation #300: Pull request #578 synchronize by sunwookim028
1m 35s sunwookim028:feature/mesh-accelerator
sunwookim028:feature/mesh-accelerator
1m 35s
fix: add float16->half type mapping for Vitis HLS backend Allo Test #1158: Pull request #578 synchronize by sunwookim028
2m 41s sunwookim028:feature/mesh-accelerator
sunwookim028:feature/mesh-accelerator
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fix: add float16->half type mapping for Vitis HLS backend Build documentation #299: Pull request #578 opened by sunwookim028
1m 52s sunwookim028:feature/mesh-accelerator
sunwookim028:feature/mesh-accelerator
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fix: add float16->half type mapping for Vitis HLS backend Allo Test #1157: Pull request #578 opened by sunwookim028
52s sunwookim028:feature/mesh-accelerator
sunwookim028:feature/mesh-accelerator
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fix: hierarchical dataflow simulator deadlock and HLS codegen (#561, #565) Allo Test #1156: Pull request #577 synchronize by sunwookim028
5m 59s sunwookim028:fix/hierarchical-dataflow-codegen
sunwookim028:fix/hierarchical-dataflow-codegen
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fix: hierarchical dataflow simulator deadlock and HLS codegen (#561, #565) Allo Test #1155: Pull request #577 opened by sunwookim028
6m 53s sunwookim028:fix/hierarchical-dataflow-codegen
sunwookim028:fix/hierarchical-dataflow-codegen
6m 53s
fix: strip MLIR %alloc names from VHLS csim output and handle ap_int in nanobind wrapper Allo Test #1154: Pull request #554 synchronize by sunwookim028
5m 58s sunwookim028:fix/vhls-mlir-percent-alloc-csim
sunwookim028:fix/vhls-mlir-percent-alloc-csim
5m 58s
Allo AIE Test Allo AIE Test #18: Scheduled
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Allo FPGA Weekly Test Allo FPGA Weekly Test #12: Scheduled
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Allo AIE Test Allo AIE Test #17: Scheduled
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Allo FPGA Weekly Test Allo FPGA Weekly Test #11: Scheduled
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Allo AIE Test Allo AIE Test #16: Scheduled
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Allo FPGA Weekly Test Allo FPGA Weekly Test #10: Scheduled
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Allo AIE Test Allo AIE Test #15: Scheduled
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[Fix] Sort dataflow kernel calls so producers precede consumers Allo Test #1153: Pull request #574 synchronize by zzzDavid
5m 53s zzzDavid:fix/dataflow-kernel-ordering
zzzDavid:fix/dataflow-kernel-ordering
5m 53s
Allo FPGA Weekly Test Allo FPGA Weekly Test #9: Scheduled
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