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fix: add float16->half type mapping for Vitis HLS backend#578

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sunwookim028 wants to merge 22 commits intocornell-zhang:mainfrom
sunwookim028:feature/mesh-accelerator
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fix: add float16->half type mapping for Vitis HLS backend#578
sunwookim028 wants to merge 22 commits intocornell-zhang:mainfrom
sunwookim028:feature/mesh-accelerator

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@sunwookim028 sunwookim028 commented Apr 13, 2026 •
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Summary

Fixes upstream issue #478 (part 3): HLS backend cannot resolve float16 types.

Changes

Added two critical type mappings for float16 support in Vitis HLS:

  1. allo/utils.py: Added `'float16' -> 'half'` to `allo2c_type` dictionary

    • Used for pybind11 C/C++ type conversion
    • Enables proper type marshalling between Python and C++

  2. allo/backend/vitis.py: Added `'f16' -> 'half'` to `ctype_map` dictionary

    • Used for Vitis HLS host code generation
    • Allows float16 scalars to be properly emitted in OpenCL host code

Verified Synthesis Results

Tested on Vitis HLS 2023.2, Xilinx U280 (xcu280-fsvh2892-2L-e), 3.33 ns clock:

Kernel Description LUT FF BRAM DSP Latency II Fmax
top_fp16_arith elementwise add + scale 3986 4233 6 5 46–48 cy 21 411 MHz
top_fp16_exp elementwise exp (hls::exp) 2668 2576 4 2 38–40 cy 13 411 MHz

Both kernels synthesize cleanly. The half type is fully synthesizable for arithmetic and transcendental ops.

Note on exp(half): hls_math.h places exp(half) in namespace hls. A companion fix in EmitVivadoHLS.cpp emits hls::exp(x) instead of exp(x) for Float16Type operands to resolve C++ overload ambiguity. The same pattern is applied to log, sqrt, sin, cos, tanh, exp2, log2, log10, abs.

Note on builder.py: A companion fix adds F16Type/BF16Type to the scalar math dispatch guard in allo/ir/builder.py, enabling allo.exp(float16_val) to lower to MLIR correctly.

Related Issues

sunwookim028 and others added 22 commits March 6, 2026 01:51
@sunwookim028
fix: resolve simulator deadlock for hierarchical dataflow regions
5e08403 
build_dataflow_simulator only injected OMP parallel sections around the
top-level function's func.call ops. Inner region kernel calls remained
sequential, causing deadlock when kernels communicate via streams.
Fix: extract OMP injection into _inject_omp_parallel_sections() helper
and apply it recursively to every function with PE kernel calls, not
just the top function.

Addresses a part of cornell-zhang#561
@sunwookim028
Fix HLS codegen for hierarchical dataflow regions (cornell-zhang#561)
83905ea 
- Added forward declarations for all functions in the HLS C++ emitter.
- Ensured hierarchical regions are correctly marked with the dataflow attribute.
- Fixed an issue where types were missing in function signatures by clearing the emitter's name table between passes.
@sunwookim028
Merge remote-tracking branch 'origin/main' into feature/mesh-accelerator
46cfa30 
# Conflicts:
#	mlir/lib/Translation/EmitVivadoHLS.cpp
@sunwookim028
fix: simulator hierarchical deadlock
ecd0180
@sunwookim028
Fix dataflow region nested kernel issues and OMP deadlock
812d222
@sunwookim028
feat: mesh architecture v1
d58130e
@sunwookim028 @claude
feat: non-blocking streams, decoupled mesh, and performance evaluatio…
0a01930 
…n framework

## Compiler extensions (allo core)
- Add try_put / try_get / empty / full non-blocking stream primitives to
  allo/ir/types.py, allo/ir/builder.py, allo/ir/infer.py and all three
  backends: Allo simulator (OMP), Vitis HLS, Tapa HLS
- Fix two HLS codegen bugs shared by EmitVivadoHLS and EmitTapaHLS:
  spurious [0] subscript on stream references and duplicate type in
  variable declarations for try_get/try_put/empty/full ops
- simulator: recursive _process_function_streams for nested kernel calls;
  auto-set OMP_MAX_ACTIVE_LEVELS=4; fix StreamPutOp ip=before_ip→replace_ip
- builder: 0-D MemRef unwrapping for scalar args in func.call
- Add @stateful annotation (maps small arrays to FFs, large to BRAM)

## New tests (12 total, all passing)
- test_stream_ops_ir / _sim / _hls: MLIR op, simulator, and HLS codegen checks
- test_stream_nb_simple: comprehensive end-to-end non-blocking stream tests
- test_decoupled_mesh: message-passing 1-CT and hierarchical 2×1 decoupled mesh

## Performance evaluation framework (tests/dataflow/mesh_perf.py)
- SimStats: wall-clock timing wrapper with OMP warmup / steady-state split
- DataflowTimingModel: analytical protocol-level cycle estimator with CT
  compute-overlap savings; produces GB/s estimates at design Fmax
- CosimHarness: reuses cached RTL synthesis (skips csynth if csynth.xml
  exists), generates run_cosim.tcl + host_cosim.cpp per testbench

## HLS synthesis scripts and results (U280, 411 MHz)
- hls_synth_streams.py: blocking (LUT=1417, II=7) vs non-blocking (+2.8% LUT)
- hls_synth_decoupled.py: 1-CT mesh (LUT=5355) and 2-CT mesh (LUT=7361)
- CSIM skipped for handshake designs (sequential execution deadlock documented)

## Documentation
- HLS_SYNTH_REPORT.md: full synthesis comparison tables and key findings
- DATAFLOW_SEMANTICS.md: execution model differences and decision matrix
- ALLO_CHANGE.md, PLAN.md, PROGRESS.md, PROGRAMMABLE_DATAFLOW.md

Co-Authored-By: Claude Sonnet 4.6 <noreply@anthropic.com>
@sunwookim028 @claude
feat: Catapult HLS synthesis working end-to-end for decoupled 2x1 mesh
01f25e2 
Key fixes to get full synthesis (codegen → go analyze → go compile →
go assembly → go extract) working on nangate-45nm_beh:

C++ emitter fixes (EmitCatapultHLS.cpp, EmitVivadoHLS.h/cpp, Utils.cpp):
- F32 type → ac_ieee_float<binary32> (nangate-45nm_beh has no native float)
- Local ac_channel declarations → 'static' (required by Catapult HIER-6)
- Stateful globals: type uses ac_ieee_float<binary32> via virtual hook
- Float array initializers: emit 0.000000f (with 'f' suffix, not double literals)
- Scalar float constants: emit 1.000000f (not (float)1.000000 cast-of-double)
- Add #include <ac_std_float.h> to kernel header
- Added emitStatefulGlobalElementType/emitFloatArrayElement virtual hooks
  in VhlsModuleEmitter for backend-specific float overrides

TCL codegen fix (catapult.py):
- Use block synthesis: solution design set <fn> -block for each sub-function
  This makes channels cross hierarchical boundaries → no HIER-10/HIER-47

Synthesis results (Catapult 2024.2, nangate-45nm, 500 MHz, 2×1 mesh):
- compute_tile latency=295 cycles, area_score=14991 (per tile)
- memory_tile latency=67 cycles, area_score=16180
- Total sequential latency=657 cycles, throughput=298 cycles

Co-Authored-By: Claude Sonnet 4.6 <noreply@anthropic.com>
@sunwookim028
docs: add non-blocking stream walkthrough, Catapult analysis, and env…
4580b7a 
… notes

- docs/source/backends/nonblocking_streams.rst: walkthrough for try_put /
  try_get / empty / full across all compiler layers (IR, simulator, Vivado
  HLS, TAPA, Catapult), with file locations and HLS cost numbers, for
  upcoming PR to cornell-zhang/allo

- CATAPULT.md: full Catapult HLS synthesis analysis for decoupled_2x1 mesh
  (latency breakdown, area, FIFO depth inference, error log with root causes
  and fixes) - kept local, not intended for upstream

- ENVIRONMENT.md: per-server setup notes (brg-zhang-xcel vs zhang-21 RHEL 8),
  LD_LIBRARY_PATH, conda env, rebuild procedure

- ppa_analysis.md: quick PPA mode usage guide for Catapult backend

- run_allo.sh: wrapper script for conda run -n allo with correct libstdc++
  path on RHEL 8 (zhang-21)

- tests/dataflow/catapult_synth_decoupled_2x1.py: synthesis script for
  decoupled_2x1 (valid-ready handshake) and arb_2to1 (arbitration, strictly
  needs non-blocking) designs; supports --mode codegen|csyn|ppa

- .gitignore: ignore mlir/build-rhel8/, hls_projects/, glibc_compat/,
  ccc/, f32_softmax_prj/, softmax_prj/, catapult_*.prj/
@sunwookim028
fix: apply stashed improvements for simulator, ip paths, and code gen…
bc8f6ef 
…eration
@sunwookim028 @claude
Merge upstream main (SPMW ops cornell-zhang#555) into feature/mesh-ac…
f8fa50c 
…celerator

Conflict in mlir/include/allo/Dialect/AlloOps.td resolved by keeping both
sets of changes: our NB stream ops (StreamTryGetOp, StreamTryPutOp,
StreamFullOp, StreamEmptyOp) and the upstream SPMW global stream ops
(StreamGlobalOp, GlobalStreamGetOp, GlobalStreamPutOp, GridMapOp).
YieldOp ParentOneOf updated to include GridMapOp (upstream change).

Co-Authored-By: Claude Sonnet 4.6 <noreply@anthropic.com>
@sunwookim028 @claude
fix: add stateful backward-compat alias after SPMW upstream merge
5595fab 
Upstream cornell-zhang#555 renamed `def stateful(dtype)` to `class Stateful`.
Add `stateful = Stateful` alias in allo/ir/types.py so existing code
using `@ stateful` annotation syntax continues to import and work.

Co-Authored-By: Claude Sonnet 4.6 <noreply@anthropic.com>
@sunwookim028 @claude
chore: remove Catapult backend and Tapa NB stream additions
89339f0 
- Delete EmitCatapultHLS.cpp, catapult.py, harness/catapult/, tests/test_catapult_hls.py,
  catapult_synth_decoupled_2x1.py, docs/source/backends/catapult.rst
- Remove Catapult header files (EmitCatapultHLS.h from allo/ and allo-c/)
- Remove EmitCatapultHLS.cpp from CAPI CMakeLists.txt
- Remove emitCatapultHls binding from AlloModule.cpp
- Revert our NB stream method additions to EmitTapaHLS.cpp (try_read/try_write)
- Drop test_nb_ops_tapa_codegen from test_stream_nb_simple.py
- Remove catapult target from customize.py and hls.py dispatch paths
- Add notes/ASIC_HLS_EXPLORATION.md preserving synthesis results for reference
- Fix docs: remove catapult.rst from toctree, clean nonblocking_streams.rst

NB stream semantics remain fully implemented for Vitis HLS (primary target).
All 5 core tests pass (3 NB stream + 2 decoupled mesh).

Co-Authored-By: Claude Sonnet 4.6 <noreply@anthropic.com>
@sunwookim028 @claude
fix: adopt upstream Stateful API, remove lowercase stateful alias
e665bbc 
Replace all `@ stateful` / `import stateful` (lowercase) with `@ Stateful`
across our test and synthesis files, and remove the backward-compat alias
`stateful = Stateful` from allo/ir/types.py added in commit 5595fab.

Co-Authored-By: Claude Sonnet 4.6 <noreply@anthropic.com>
@sunwookim028 @claude
chore: add CLAUDE.md, move STATE.md to root, commit issues/ and notes/
039e163 
- CLAUDE.md: project agent instructions extending upstream AGENTS.md
  Includes project management conventions for updating issues/ and notes/
- STATE.md: project dashboard at root (vision, task board, dependencies)
- notes/: move 9 root-level doc files here (git renamed; untracked copies
  already existed in notes/, so git rm root + git add notes/ resolves conflicts)
- issues/: first commit of task tracking files (ISSUE-001 through ISSUE-007)
- issues/STATE.md removed (superseded by root STATE.md)

Co-Authored-By: Claude Sonnet 4.6 <noreply@anthropic.com>
@sunwookim028 @claude
docs: update STATE.md and issues to reflect session end state
cd16345 
- STATE.md: mark PR cornell-zhang#577 CI as PASSED, record stateful→Stateful and
  project structure changes in Completed This Cycle
- ISSUE-003: update status to NEEDS-REVIEW (CI PASSED)
- ISSUE-004: record alias removal (e665bbc) superseding temp alias (5595fab)

Co-Authored-By: Claude Sonnet 4.6 <noreply@anthropic.com>
@sunwookim028
fix: add float16->half type mapping for Vitis HLS backend
ce1e0b3 
Resolves part of upstream issue cornell-zhang#478: HLS backend cannot resolve float16 types.

Two critical mappings were missing:
1. allo/utils.py: Add 'float16' -> 'half' to allo2c_type dict
   Used for pybind11 C/C++ type conversion
2. allo/backend/vitis.py: Add 'f16' -> 'half' to ctype_map dict
   Used for Vitis HLS host code generation

With these changes, float16 kernels can now be compiled to Vitis HLS
without 'Fail to resolve ctype half' error.

Addresses: cornell-zhang#478 (part 3: HLS backend type resolution)
@sunwookim028 @claude
docs: add fp16 HLS notes, issues 008-010, code quality + scratch path…
853d5dd 
… to CLAUDE.md

- notes/FP16_VITIS_HLS.md: knowledge file covering float16 support status in Vitis
  HLS backend (what works, what is unverified, known gaps)
- issues/ISSUE-008: write + run csyn verification test for float16 arithmetic + exp
- issues/ISSUE-009: fix scalar exp dispatch in builder.py for float16 (F16Type missing)
- issues/ISSUE-010: conditional emitter fix for exp(half) if csyn reveals HLS issue
- STATE.md: add ISSUE-008/009/010 rows and dep graph
- CLAUDE.md: add Code Quality rule (follow established practices, no ad-hoc patching)
  and Filesystem note (/scratch/sk3463/ for large outputs)

Co-Authored-By: Claude Haiku 4.5 <noreply@anthropic.com>
@sunwookim028 @claude
fix: revert TapaModuleEmitter NB-stream override decls to unblock CI
cc1963a 
The override declarations for emitStreamTryGet/Put/Empty/Full were added
to EmitTapaHLS.h in 0a01930 but their implementations were never committed
to EmitTapaHLS.cpp.  This caused undefined-reference linker errors when
building libAlloMLIRAggregateCAPI.so in CI.

Restore EmitTapaHLS.h and EmitTapaHLS.cpp to upstream main state.  The
base class (EmitBaseHLS) already provides empty default implementations
for all four ops, so Tapa HLS output is unaffected.  NB-stream support
for the Tapa backend is deferred to a separate task.

Co-Authored-By: Claude Sonnet 4.6 <noreply@anthropic.com>
@sunwookim028 @claude
fix: fp16 scalar math dispatch and hls:: namespace for half ops (ISSU…
246e704 
…E-009/010)

allo/ir/builder.py:
- Add F16Type and BF16Type to the scalar math dispatch type guard so that
  allo.exp(float16) correctly lowers to math.ExpOp instead of being
  rejected as a non-scalar type.

mlir/lib/Translation/EmitVivadoHLS.cpp:
- Add isHalf() helper that checks if an op's operand is Float16Type.
- Route all scalar math unary ops (exp, log, sqrt, sin, cos, tanh,
  exp2, log2, log10, abs) through hls::<fn> when the operand is half.
  Rationale: hls_math.h places exp(half) in namespace hls; the bare
  call is ambiguous with C double / C++ float overloads and fails csyn.

Both issues verified with Vitis HLS 2023.2 on U280 (see HLS_SYNTH_REPORT.md).

Co-Authored-By: Claude Sonnet 4.6 <noreply@anthropic.com>
@sunwookim028 @claude
chore: add license headers to all files changed vs origin/main
10d3753 
Satisfies the upstream license header check (check_license_header.py).
Covers: CLAUDE.md, STATE.md, run_allo.sh, issues/*.md, notes/*.md,
and tests/dataflow/*.py added on this branch.

Co-Authored-By: Claude Sonnet 4.6 <noreply@anthropic.com>
@sunwookim028 @claude
chore: exclude fork-local mgmt files from license check; keep test he…
06ce561 
…aders

check_license_header.py: skip issues/, notes/, STATE.md, CLAUDE.md,
run_allo.sh — these are fork-local project management files that are
not intended for upstream and do not need the Allo license header.

Strip the incorrectly added headers from those files.  License headers
on tests/dataflow/*.py (legitimate upstream contributions) are kept.

Co-Authored-By: Claude Sonnet 4.6 <noreply@anthropic.com>
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[BUG] float16 and bfloat16 missing critical operators

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