DataflowBuildConfig Documentation

Build configuration to be passed to the build_dataflow function. Can be serialized into or de-serialized from JSON files for persistence. See list of attributes below for more information on the build configuration.

Enumerations

🏷️ AutoFIFOSizingMethod

Select the type of automatic FIFO sizing strategy.

Option	Value
CHARACTERIZE	'characterize'
LARGEFIFO_RTLSIM	'largefifo_rtlsim'

🏷️ DataflowOutputType

Output product types that can be generated by build_dataflow.

Option	Value
STITCHED_IP	'stitched_ip'
ESTIMATE_REPORTS	'estimate_reports'
OOC_SYNTH	'out_of_context_synth'
RTLSIM_PERFORMANCE	'rtlsim_performance'
BITFILE	'bitfile'
PYNQ_DRIVER	'pynq_driver'
CPP_DRIVER	'cpp_driver'
DEPLOYMENT_PACKAGE	'deployment_package'

🏷️ FpgaMemoryType

Memory Type used by the FPGA to store input/output data.

Option	Value
DEFAULT	'default'
HOST_MEM	'host_memory'

🏷️ LargeFIFOMemStyle

Type of memory resource to use for large FIFOs.

Option	Value
AUTO	'auto'
BRAM	'block'
LUTRAM	'distributed'
URAM	'ultra'

🏷️ LogLevel

Log levels printed on the commandline for the build process.

Option	Value
NONE	'NONE'
DEBUG	'DEBUG'
INFO	'INFO'
WARNING	'WARNING'
ERROR	'ERROR'
CRITICAL	'CRITICAL'

🏷️ ShellFlowType

For builds that produce a bitfile, select the shell flow that will integrate the FINN-generated accelerator.

Option	Value
VIVADO_ZYNQ	'vivado_zynq'
VITIS_ALVEO	'vitis_alveo'

🏷️ VerificationStepType

Steps at which FINN ONNX execution can be launched for verification.

Option	Value
QONNX_TO_FINN_PYTHON	'finn_onnx_python'
TIDY_UP_PYTHON	'initial_python'
STREAMLINED_PYTHON	'streamlined_python'
FOLDED_HLS_CPPSIM	'folded_hls_cppsim'
NODE_BY_NODE_RTLSIM	'node_by_node_rtlsim'
STITCHED_IP_RTLSIM	'stitched_ip_rtlsim'
PASSES_FRONTEND	'passes_frontend'

🏷️ VitisOptStrategy

Values applicable to VitisBuild optimization strategy.

Option	Value
DEFAULT	'0'
POWER	'1'
PERFORMANCE	'2'
PERFORMANCE_BEST	'3'
SIZE	's'
BUILD_SPEED	'quick'

Configuration Fields

📝 auto_fifo_depths

Property	Value
Type	bool
Default	True
Description	Whether FIFO depths will be set automatically. Involves running stitched rtlsim and can take a long time. If set to False, the folding_config_file can be used to specify sizes for each FIFO.

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📝 auto_fifo_strategy

Property	Value
Type	AutoFIFOSizingMethod
Default	AutoFIFOSizingMethod.LARGEFIFO_RTLSIM
Description	(Only relevant when auto_fifo_depths is enabled) Select which method will be used for setting the FIFO sizes.

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📝 board

Property	Value
Type	Optional[str]
Default	None
Description	(Only needed for generating full bitfiles with shell integration) Target board, e.g. "Pynq-Z1" or "U250".

---

📝 config_path

Property	Value
Type	Path | None
Default	None
Description	Path to the config from which this object was created. Can be left on None for cases in which "finn run" is used, but should otherwise be set to correctly infer flow-config relative paths (like specialization JSONs, etc.)

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📝 console_log_level

Property	Value
Type	LogLevel
Default	LogLevel.ERROR
Description	Log level to be used on the command line for finn-plus internal logging. This is different from the log level used for build_dataflow.log, which is controlled using the verbose flag.

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📝 cpp_driver_version

Property	Value
Type	str
Default	'latest'
Description	(Only relevant if CPP_DRIVER output product is enabled) Selects C++ driver version. If set to "latest", newest version will be used. If set to commit hash, specified version will be used.

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📝 default_swg_exception

Property	Value
Type	bool
Default	False
Description	(Only relevant if auto_fifo_strategy = LARGEFIFO_RTLSIM) Call CapConvolutionFIFODepths in InsertAndSetFIFODepths transform to make convolution FIFOs smaller where appropriate.

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📝 enable_build_pdb_debug

Property	Value
Type	bool
Default	False
Description	Whether pdb postmortem debugging will be launched when the build fails.

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📝 enable_exception_snapshots

Property	Value
Type	bool
Default	False
Description	When set to true, decorates every step in the build flow with a function that catches exceptions, snapshots the ONNX model, the config and the build log, saves them into the crash_reports directory in output_dir, and re-raises the exception for further error handling. By default this does not save FINN itself; however any step can still be manually decorated to do so (see finn/utils/exception_snapshot.py).

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📝 enable_hw_debug

Property	Value
Type	bool
Default	False
Description	Whether hardware debugging will be enabled (e.g. ILA cores inserted to debug signals in the generated hardware).

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📝 enable_instrumentation

Property	Value
Type	bool
Default	False
Description	Whether the accelerator will be simulated and synthesized with an instrumentation wrapper attached to accurately measure performance.

---

📝 experiments_config_path

Property	Value
Type	Optional[str]
Default	None
Description	If set, appends experiments_config to settings file during driver generation

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📝 fifosim_input_throttle

Property	Value
Type	bool
Default	True
Description	(Only relevant if auto_fifo_strategy = LARGEFIFO_RTLSIM) Enable input throttling for simulation-based FIFO sizing.

---

📝 fifosim_n_inferences

Property	Value
Type	int
Default	2
Description	(Only relevant if auto_fifo_strategy = LARGEFIFO_RTLSIM) Manually specify the number of inferences for simulation-based FIFO sizing

---

📝 fifosim_save_waveform

Property	Value
Type	bool
Default	False
Description	(Only relevant if auto_fifo_strategy = LARGEFIFO_RTLSIM) Enable saving waveforms from simulation-based FIFO sizing.

---

📝 folding_config_file

Property	Value
Type	Path | None
Default	None
Description	(Optional) Path to configuration JSON file. May include parallelization, FIFO sizes, RAM and implementation style attributes and so on. If the parallelization attributes (PE, SIMD) are part of the config, this will override the automatically generated parallelization attributes inferred from target_fps (if any) Will be applied with :py:mod:finn.transformation.general.ApplyConfig

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📝 folding_two_pass_relaxation

Property	Value
Type	bool
Default	True
Description	(Only relevant if target_fps is set) Use two-pass relaxation for folding. If enabled, parallelization will internally run a second time if the target cycles from the first pass could not be achieved, instead using the achievable target to obtain a balanced pipeline. If disabled, this can be useful for decreasing the latency (even though throughput won't increase).

---

📝 fpga_memory

Property	Value
Type	FpgaMemoryType
Default	FpgaMemoryType.DEFAULT
Description	(Only relevant when shell_flow_type = VITIS_ALVEO) Select FPGA memory type. Can be used to use host memory for input/output data instead of DDR or HBM memory

---

📝 fpga_part

Property	Value
Type	Optional[str]
Default	None
Description	(Only needed when board not specified) Target Xilinx FPGA part, e.g. "xc7z020clg400-1".

---

📝 generate_outputs

Property	Value
Type	Optional[list[DataflowOutputType]]
Default	field(default_factory=lambda : [DataflowOutputType.STITCHED_IP, DataflowOutputType.ESTIMATE_REPORTS, DataflowOutputType.OOC_SYNTH, DataflowOutputType.RTLSIM_PERFORMANCE, DataflowOutputType.BITFILE, DataflowOutputType.PYNQ_DRIVER, DataflowOutputType.CPP_DRIVER, DataflowOutputType.DEPLOYMENT_PACKAGE])
Description	Which output(s) to generate from the build flow. See documentation of DataflowOutputType for available options.

---

📝 hls_clk_period_ns

Property	Value
Type	Optional[float]
Default	None
Description	(Optional) Target clock frequency (in nanoseconds) for Vitis HLS synthesis. e.g. hls_clk_period_ns=5.0 will target a 200 MHz clock. If not specified it will default to synth_clk_period_ns

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📝 infer_shuffle_skip_first

Property	Value
Type	bool
Default	True
Description	Whether to skip converting the first Transpose node to a Shuffle layer. This is useful for image classification networks where the first transpose converts NCHW to NHWC layout for data preprocessing. Enabled by default.

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📝 instrumentation_no_dma

Property	Value
Type	Optional[bool]
Default	False
Description	If enable_instrumentation is True, one can disable the DMA with this flag

---

📝 large_fifo_mem_style

Property	Value
Type	LargeFIFOMemStyle
Default	LargeFIFOMemStyle.AUTO
Description	(Only relevant when auto_fifo_depths is enabled) Memory resource type for large FIFOs.

---

📝 layouts_config_file

Property	Value
Type	Path | None
Default	None
Description	(Optional) Path to configuration YAML file listing layout assumptions and conversion (permutation) for global model inputs and outputs.

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📝 live_fifo_sizing

Property	Value
Type	bool
Default	False
Description	Enables experimental live FIFO sizing on the FPGA.

---

📝 loop_body_hierarchy

Property	Value
Type	Optional[List[List[str]]]
Default	None
Description	A List of strings that specify the PyTorch metadata hierarchy to be used for the loop body hierarchy. Each item in the list should be a string that represents a level in the hierarchy.

---

📝 loop_body_range

Property	Value
Type	Optional[List[Any]]
Default	None
Description	A list of a start and an end node to mark the loop body subgraph For this node range, the PyTorch metadata hierarchy will be simulated TODO: this argument will be replaced or extended when there is a way to preserve node metadata from the PyTorch model (e.g. from dynamo exporter)

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📝 max_multithreshold_bit_width

Property	Value
Type	int
Default	8
Description	Control which Quant nodes of the QONNX format get converted to FINN's MultiThreshold nodes. This only affects Quant nodes in the activation path. Quant nodes, which define a bit width larger than max_multithreshold_bit_width are not converted to MultiThreshold nodes and a warning is raised instead.

---

📝 minimize_bit_width

Property	Value
Type	bool
Default	True
Description	Whether optimizations that minimize the bit width of the weights and accumulator will be applied. Because this optimization relies on the the values of the weights, it will only be applied if runtime- writeable weights is not enabled.

---

📝 mlo

Property	Value
Type	bool
Default	False
Description	If set to True, the FINN compiler tries to create an MLO design based on loop_body_hierarchy and loop_body_range

---

📝 model_path

Property	Value
Type	Path | None
Default	None
Description	Path to the model. This CAN be set by the startup, but must not necessarily.

---

📝 mvau_wwidth_max

Property	Value
Type	int
Default	36
Description	(Only relevant if target_fps is set) Control the maximum width of the per-PE MVAU stream while exploring the parallelization attributes to reach target_fps. Set this to a large value (e.g. 10000) if targeting full unfolding or very high performance.

---

📝 output_dir

Property	Value
Type	str | Path
Default	'finn_build_output'
Description	Directory where the final build outputs will be written into

---

📝 rtlsim_batch_size

Property	Value
Type	int
Default	1
Description	Control the number of input frames for rtlsim performance measurement.

---

📝 rtlsim_use_vivado_comps

Property	Value
Type	bool
Default	True
Description	If set to True, FIFOs with impl_style=vivado will be kept during rtlsim, otherwise they will be replaced by RTL implementations.

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📝 save_intermediate_models

Property	Value
Type	bool
Default	True
Description	Whether intermediate ONNX files will be saved during the build process. These can be useful for debugging if the build fails.

---

📝 shell_flow_type

Property	Value
Type	Optional[ShellFlowType]
Default	None
Description	(Only needed for generating full bitfiles with shell integration) Target shell flow, see documentation of ShellFlowType for options.

---

📝 signature

Property	Value
Type	Optional[list[int]]
Default	None
Description	(Optional) Insert a signature node to the stitched-IP to read/write information to the design: e.g. Customer signature, application signature, version

---

📝 specialize_layers_config_file

Property	Value
Type	Path | None
Default	None
Description	(Optional) Path to configuration JSON file in which user can specify a preferred implementation style (HLS or RTL) for each node. The SpecializeLayers transformation picks up these settings and if possible fulfills the desired implementation style for each layer by converting the node into its HLS or RTL variant. Will be applied with :py:mod:finn.transformation.general.ApplyConfig

---

📝 split_large_fifos

Property	Value
Type	bool
Default	False
Description	Whether FIFO nodes with depth larger than 32768 will be split. Allow to configure very large FIFOs in the folding_config_file.

---

📝 standalone_thresholds

Property	Value
Type	bool
Default	False
Description	Whether thresholding layers (which implement quantized activations in FINN) will be implemented as standalone HW layers, instead of being part of MatrixVectorActivation layer. This gives larger flexibility, and makes it possible to have runtime-writable thresholds.

---

📝 start_step

Property	Value
Type	Optional[str]
Default	None
Description	(Optional) Start build from this step, loading the intermediate model generated from the previous step (save_intermediate_models must be enabled).

---

📝 steps

Property	Value
Type	Optional[list[Any]]
Default	None
Description	(Optional) Only run the steps in the list. If not set, run default steps. See default_build_dataflow_steps for the default list of steps. When specified: Each item can either be a string, or a function (does not apply to json serialized configs) and does the following: - strings are resolved to functions from the default list - functions are called with (model, DataflowBuildConfig) as args

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📝 stitched_ip_gen_dcp

Property	Value
Type	bool
Default	False
Description	Run synthesis to generate a .dcp for the stitched-IP output product. This can make it easier to treat it as a standalone artifact without requiring the full list of layer IP build directories. By default, synthesis will not run.

---

📝 stop_step

Property	Value
Type	Optional[str]
Default	None
Description	(Optional) Stop build at this step.

---

📝 synth_clk_period_ns

Property	Value
Type	float
Default	10.0
Description	Target clock frequency (in nanoseconds) for Vivado synthesis. e.g. synth_clk_period_ns=5.0 will target a 200 MHz clock. If hls_clk_period_ns is not specified it will default to this value.

---

📝 target_fps

Property	Value
Type	Optional[int]
Default	None
Description	(Optional) Target inference performance in frames per second. Note that target may not be achievable due to specific layer constraints, or due to resource limitations of the FPGA. If parallelization attributes are specified as part of folding_config_file that will override the target_fps setting here.

---

📝 validation_dataset

Property	Value
Type	Optional[str]
Default	None
Description	(Optional) Specify validation dataset to be used for deployment of the PYNQ driver.

---

📝 verbose

Property	Value
Type	bool
Default	False
Description	When True, additional information (level = DEBUG) will be written to the log file. Otherwise, this additional information will be suppressed (level = INFO).

---

📝 verification_atol

Property	Value
Type	float
Default	0.001
Description	Set verification tolerance: absolute error per output element.

---

📝 verification_mean_atol

Property	Value
Type	float
Default	0.001
Description	Set verification tolerance: mean absolute error over output elements of each frame.

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📝 verification_mean_rtol

Property	Value
Type	float
Default	0.1
Description	Set verification tolerance: mean relative error over output elements of each frame.

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📝 verification_rtol

Property	Value
Type	float
Default	1e-05
Description	Set verification tolerance: relative error per output element. This is added to the absolute tolerance (as computed by numpy.isclose).

---

📝 verify_expected_output_npy

Property	Value
Type	str | Path
Default	'expected_output.npy'
Description	(Only relevant if verify_steps is set) Name of .npy file that will be used as the expected output for verification.

---

📝 verify_input_npy

Property	Value
Type	str | Path
Default	'input.npy'
Description	(Only relevant if verify_steps is set) Name of .npy file that will be used as the input for verification.

---

📝 verify_save_full_context

Property	Value
Type	bool
Default	False
Description	(Only relevant if verify_steps is set) Save full execution context for each of the verify_steps. By default, only the top-level graph output is saved. This option also enables detailed activation tensor statistics logging.

---

📝 verify_save_rtlsim_waveforms

Property	Value
Type	bool
Default	False
Description	(Only relevant if verify_steps is set or RTLSIM_PERFORMANCE output product is enabled) Save .vcd waveforms from rtlsim under reports. By default, waveforms won't be saved.

---

📝 verify_steps

Property	Value
Type	Optional[list[VerificationStepType]]
Default	None
Description	(Optional) At which steps the generated intermediate output model will be verified. See documentation of VerificationStepType for available options.

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📝 vitis_floorplan_file

Property	Value
Type	Optional[str]
Default	None
Description	(Optional, only relevant when shell_flow_type = VITIS_ALVEO) Path to JSON config file assigning each layer to an SLR. Only relevant when shell_flow_type = [ShellFlowType](#🏷️-shellflowtype).VITIS_ALVEO Will be applied with :py:mod:finn.transformation.general.ApplyConfig

---

📝 vitis_opt_strategy

Property	Value
Type	VitisOptStrategy
Default	VitisOptStrategy.DEFAULT
Description	(Only relevant when shell_flow_type = VITIS_ALVEO) Select Vitis optimization strategy.

---

📝 vitis_platform

Property	Value
Type	Optional[str]
Default	None
Description	(Optional, only relevant when shell_flow_type = VITIS_ALVEO) Which Vitis platform will be used, e.g. "xilinx_u250_xdma_201830_2". If not specified but "board" is specified, will use the FINN default (if any) for that Alveo board.

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📝 vivado_power_simulate_activity

Property	Value
Type	bool
Default	True
Description	(Only relevant if step_vivado_power_estimation is run) Whether to simulate the switching activity of the design for Vivado power estimation. If set to False, use only a fixed set of static toggle rates and static probabilities. If set to True, use simulated activity to generate an additional power report.

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📝 vivado_power_simulation_type

Property	Value
Type	Literal['timing', 'functional']
Default	'functional'
Description	(Only relevant for step_vivado_power_estimation if vivado_power_simulate_activity is True) Whether to use "functional" or "timing" simulation for Vivado power estimation.

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Last updated: 2026-04-17 10:01:48 UTC by GitHub Actions Generated from commit: e2d2542fcca2b072d15d1a781ab589ef4dca248b