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chore: risc-v dialects now prefer size-64 bitvectors instead of arbitrary integers - #1466

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regehr merged 12 commits into
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regehr/riscv-li-64-bits
Sep 15, 2026
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regehr merged 12 commits into
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regehr/riscv-li-64-bits

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@regehr regehr commented Sep 14, 2026

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in upstream dialects like Arith and LLVM, we're forced to deal with literal constants whose attribute width differs from the width of the operation, making things potentially confusing and error-prone.

in our own RISC-V dialects, we're not constrained by upstream, so this PR is a simplification removing that degree of freedom and furthermore just centralizing on i64 as the internal data representation for our RISC-V dialects. this removes some possibilities for errors around signed/unsigned conversions and I think it's a good change overall.

@regehr regehr self-assigned this Sep 14, 2026
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regehr marked this pull request as draft September 14, 2026 14:25
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regehr marked this pull request as ready for review September 14, 2026 14:56
@tobiasgrosser tobiasgrosser added the RISCV The RISCV Dialect label Sep 14, 2026

@tobiasgrosser tobiasgrosser left a comment

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I had initially thought to just add verifier to check that the type is an i64. This is a bit more involved, but seems to make the API a bit simpler. For BitVec constants, there is a nice syntax.

I am happy with this. Let's see what @math-fehr says.

Comment thread Test/RISCV/mem-imm-width-not-i64.mlir Outdated
Comment thread UnitTest/FoldDecision.lean Outdated
Comment thread Veir/Dialects/Builtin/Properties.lean Outdated
Comment thread Veir/Passes/InstructionSelection/RISCV64.lean Outdated
Comment thread Veir/Passes/RISCVCombines/Combine.lean Outdated

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I found nothing else; LGTM!

@math-fehr math-fehr left a comment

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Tobias pointed most of the issues already, besides that this is good to me!

Comment thread Veir/Dialects/Builtin/Properties.lean Outdated
@regehr
regehr enabled auto-merge September 15, 2026 04:39
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regehr added this pull request to the merge queue Sep 15, 2026
Merged via the queue into main with commit 72e59dd Sep 15, 2026
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@regehr
regehr deleted the regehr/riscv-li-64-bits branch September 15, 2026 04:49
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4 participants