chore: risc-v dialects now prefer size-64 bitvectors instead of arbitrary integers

Test/Passes/InstructionSelection/RISCV64/const.mlir

@@ -7,30 +7,30 @@
         // CHECK: %[[A:.*]] = "riscv.li"() <{"value" = -1 : i64}> : () -> !riscv.reg
         // CHECK-NEXT: {{.*}} = "builtin.unrealized_conversion_cast"(%[[A]]) : (!riscv.reg) -> i64
         %c2 = "llvm.mlir.constant"() <{"value" = -1 : i32 }> : () -> i32
-        // CHECK: %[[A:.*]] = "riscv.li"() <{"value" = -1 : i32}> : () -> !riscv.reg
+        // CHECK: %[[A:.*]] = "riscv.li"() <{"value" = -1 : i64}> : () -> !riscv.reg
         // CHECK-NEXT: {{.*}} = "builtin.unrealized_conversion_cast"(%[[A]]) : (!riscv.reg) -> i32
         %c3 = "llvm.mlir.constant"() <{"value" = -1 : i8 }> : () -> i8
-        // CHECK: %[[A:.*]] = "riscv.li"() <{"value" = -1 : i8}> : () -> !riscv.reg
+        // CHECK: %[[A:.*]] = "riscv.li"() <{"value" = -1 : i64}> : () -> !riscv.reg
         // CHECK-NEXT: {{.*}} = "builtin.unrealized_conversion_cast"(%[[A]]) : (!riscv.reg) -> i8
         %c4 = "llvm.mlir.constant"() <{"value" = -1 : i1 }> : () -> i1
-        // CHECK: %[[A:.*]] = "riscv.li"() <{"value" = -1 : i1}> : () -> !riscv.reg
+        // CHECK: %[[A:.*]] = "riscv.li"() <{"value" = -1 : i64}> : () -> !riscv.reg
         // CHECK-NEXT: {{.*}} = "builtin.unrealized_conversion_cast"(%[[A]]) : (!riscv.reg) -> i1
         // An attribute wider than the result carries bits that are not part of the
         // value: `300 : i32` in an i8 result is 44.
         %c5 = "llvm.mlir.constant"() <{"value" = 300 : i32 }> : () -> i8
-        // CHECK: %[[A:.*]] = "riscv.li"() <{"value" = 44 : i32}> : () -> !riscv.reg
+        // CHECK: %[[A:.*]] = "riscv.li"() <{"value" = 44 : i64}> : () -> !riscv.reg
         // CHECK-NEXT: {{.*}} = "builtin.unrealized_conversion_cast"(%[[A]]) : (!riscv.reg) -> i8
         // An i1 attribute is zero-extended, so `-1 : i1` in an i64 result is 1.
         %c6 = "llvm.mlir.constant"() <{"value" = -1 : i1 }> : () -> i64
-        // CHECK: %[[A:.*]] = "riscv.li"() <{"value" = 1 : i1}> : () -> !riscv.reg
+        // CHECK: %[[A:.*]] = "riscv.li"() <{"value" = 1 : i64}> : () -> !riscv.reg
         // CHECK-NEXT: {{.*}} = "builtin.unrealized_conversion_cast"(%[[A]]) : (!riscv.reg) -> i64
         // A non-i1 attribute is sign-extended, so `255 : i8` in an i64 result is -1.
         %c7 = "llvm.mlir.constant"() <{"value" = 255 : i8 }> : () -> i64
-        // CHECK: %[[A:.*]] = "riscv.li"() <{"value" = -1 : i8}> : () -> !riscv.reg
+        // CHECK: %[[A:.*]] = "riscv.li"() <{"value" = -1 : i64}> : () -> !riscv.reg
         // CHECK-NEXT: {{.*}} = "builtin.unrealized_conversion_cast"(%[[A]]) : (!riscv.reg) -> i64
         // Likewise `4294967295 : i32` in an i64 result is -1.
         %c8 = "llvm.mlir.constant"() <{"value" = 4294967295 : i32 }> : () -> i64
-        // CHECK: %[[A:.*]] = "riscv.li"() <{"value" = -1 : i32}> : () -> !riscv.reg
+        // CHECK: %[[A:.*]] = "riscv.li"() <{"value" = -1 : i64}> : () -> !riscv.reg
         // CHECK-NEXT: {{.*}} = "builtin.unrealized_conversion_cast"(%[[A]]) : (!riscv.reg) -> i64
         "test.test"(%c1) : (i64) -> ()
         "test.test"(%c2) : (i32) -> ()

Test/Passes/InstructionSelection/RISCV64/li.mlir

@@ -15,7 +15,7 @@
 
     "func.func"()  <{function_type = () -> (), sym_name = "bar"}> ({
         %one = "llvm.mlir.constant"() <{ "value" = 1 : i32 }> : () -> i32
-        // CHECK: [[C:%.*]] = "riscv.li"() <{"value" = 1 : i32}> : () -> !riscv.reg
+        // CHECK: [[C:%.*]] = "riscv.li"() <{"value" = 1 : i64}> : () -> !riscv.reg
         // CHECK-NEXT: %{{.*}} = "builtin.unrealized_conversion_cast"([[C]]) : (!riscv.reg) -> i32
         "test.test"(%one) : (i32) -> ()
         "func.return"() : () -> ()

Test/Passes/InstructionSelection/RISCV64/sext.mlir

@@ -20,12 +20,12 @@
         // CHECK-NEXT:      %[[M:.*]] = "riscv.sextw"(%[[L]]) : (!riscv.reg) -> !riscv.reg
         // CHECK-NEXT:      %[[N:.*]] = "builtin.unrealized_conversion_cast"(%[[M]]) : (!riscv.reg) -> i64
         // CHECK-NEXT:      %[[O:.*]] = "builtin.unrealized_conversion_cast"([[A]]) : (i1) -> !riscv.reg
-        // CHECK-NEXT:      %[[P:.*]] = "riscv.slli"(%[[O]]) <{"value" = 63 : i6}> : (!riscv.reg) -> !riscv.reg
-        // CHECK-NEXT:      %[[Q:.*]] = "riscv.srai"(%[[P]]) <{"value" = 63 : i6}> : (!riscv.reg) -> !riscv.reg
+        // CHECK-NEXT:      %[[P:.*]] = "riscv.slli"(%[[O]]) <{"value" = 63 : i64}> : (!riscv.reg) -> !riscv.reg
+        // CHECK-NEXT:      %[[Q:.*]] = "riscv.srai"(%[[P]]) <{"value" = 63 : i64}> : (!riscv.reg) -> !riscv.reg
         // CHECK-NEXT:      %[[R:.*]] = "builtin.unrealized_conversion_cast"(%[[Q]]) : (!riscv.reg) -> i64
         // CHECK-NEXT:      %[[S:.*]] = "builtin.unrealized_conversion_cast"([[A]]) : (i1) -> !riscv.reg
-        // CHECK-NEXT:      %[[T:.*]] = "riscv.slli"(%[[S]]) <{"value" = 63 : i6}> : (!riscv.reg) -> !riscv.reg
-        // CHECK-NEXT:      %[[U:.*]] = "riscv.srai"(%[[T]]) <{"value" = 63 : i6}> : (!riscv.reg) -> !riscv.reg
+        // CHECK-NEXT:      %[[T:.*]] = "riscv.slli"(%[[S]]) <{"value" = 63 : i64}> : (!riscv.reg) -> !riscv.reg
+        // CHECK-NEXT:      %[[U:.*]] = "riscv.srai"(%[[T]]) <{"value" = 63 : i64}> : (!riscv.reg) -> !riscv.reg
         // CHECK-NEXT:      %[[V:.*]] = "builtin.unrealized_conversion_cast"(%[[U]]) : (!riscv.reg) -> i32
         // CHECK-NEXT:      %[[W:.*]] = "builtin.unrealized_conversion_cast"([[E]]) : (i8) -> !riscv.reg
         // CHECK-NEXT:      %[[X:.*]] = "riscv.sextb"(%[[W]]) : (!riscv.reg) -> !riscv.reg

Test/RISCV/mem-imm-width-not-i64.mlir

@@ -0,0 +1,11 @@
+// RUN: not veir-opt %s 2>&1 | filecheck %s
+
+"builtin.module"() ({
+  "func.func"() <{sym_name = "main", function_type = () -> !riscv.reg}> ({
+    %a = "riscv.li"() <{ "value" = 0 : i64 }> : () -> !riscv.reg
+    %y = "riscv.ld"(%a) <{ "value" = 8 : i12 }> : (!riscv.reg) -> !riscv.reg
+    "func.return"(%y) : (!riscv.reg) -> ()
+  }) : () -> ()
+}) : () -> ()
+
+// CHECK: error: RISC-V memory operation: expected 'value' to be a 64-bit signless integer attribute, but got i12

Test/Verifier/riscv_stack_alloca_alignment_width_not_i64.mlir

@@ -0,0 +1,12 @@
+// RUN: not veir-opt %s 2>&1 | filecheck %s
+
+// As `riscv_stack_alloca_size_width_not_i64.mlir`, for `alignment`.
+
+"builtin.module"() ({
+  "func.func"() <{function_type = () -> (), sym_name = "main"}> ({
+    %slot = "riscv_stack.alloca"() <{size = 8 : i64, alignment = 8 : i16}> : () -> !riscv.reg
+    "func.return"() : () -> ()
+  }) : () -> ()
+}) : () -> ()
+
+// CHECK: error: alloca: expected 'alignment' to be a 64-bit signless integer attribute, but got i16

Test/Verifier/riscv_stack_alloca_size_width_not_i64.mlir

@@ -0,0 +1,10 @@
+// RUN: not veir-opt %s 2>&1 | filecheck %s
+
+"builtin.module"() ({
+  "func.func"() <{function_type = () -> (), sym_name = "main"}> ({
+    %slot = "riscv_stack.alloca"() <{size = 8 : i32, alignment = 8 : i64}> : () -> !riscv.reg
+    "func.return"() : () -> ()
+  }) : () -> ()
+}) : () -> ()
+
+// CHECK: error: alloca: expected 'size' to be a 64-bit signless integer attribute, but got i32

UnitTest/FoldDecision.lean

@@ -80,7 +80,7 @@ private def testRiscvConstantMaterialization : String := Id.run do
   let value : RuntimeValue := .reg ⟨BitVec.ofInt 64 (-77)⟩
   match (.riscv .add : OpCode).materializeConstant value regType with
   | some ⟨.riscv .li, props⟩ =>
-    if props.value ≠ IntegerAttr.mk (-77) (IntegerType.mk 64) then
+    if props.value ≠ BitVec.ofInt 64 (-77) then
       return "RISC-V materialized the wrong immediate"
     return "ok"
   | _ => return "RISC-V did not materialize riscv.li"

Veir/Dialects/Builtin/Properties.lean

@@ -24,6 +24,26 @@ def UnregisteredProperties.fromAttrDict (attrDict : Std.HashMap ByteArray Attrib
     Except String UnregisteredProperties :=
   .ok { opName := .empty, properties := DictionaryAttr.fromArray attrDict.toArray }
 
+/--
+  Read a required integer attribute that must be declared `i64`, returning the
+  value it denotes as a `BitVec 64`.
+-/
+def getI64Attr (what key : String) (attrDict : Std.HashMap ByteArray Attribute) :
+    Except String (BitVec 64) := do
+  let some attr := attrDict[key.toUTF8]?
+    | throw s!"{what}: missing '{key}' property"
+  let .integerAttr intAttr := attr
+    | throw s!"{what}: expected '{key}' to be an integer attribute, but got {attr}"
+  if intAttr.type.bitwidth ≠ 64 then
+    throw s!"{what}: expected '{key}' to be a 64-bit signless integer attribute, but got i{intAttr.type.bitwidth}"
+  if intAttr.value < -(2 ^ 63) ∨ 2 ^ 64 ≤ intAttr.value then
+    throw s!"{what}: '{key}' value {intAttr.value} does not fit in i64"
+  return BitVec.ofInt 64 intAttr.value
+
+/-- Re-encode a `getI64Attr` value as the `i64` attribute it is printed as. -/
+def i64Attr (value : BitVec 64) : Attribute :=
+  .integerAttr (IntegerAttr.mk value.toInt (IntegerType.mk 64))
+
 def getUnitAttr (key : String) (attrDict : Std.HashMap ByteArray Attribute) :
     Except String Bool := do
   match attrDict[key.toUTF8]? with