rvp for rv32/rv64 by chihminchao · Pull Request #2246 · riscv-software-src/riscv-isa-sim

chihminchao · 2026-03-11T04:12:26Z

The PR merges the works, #2210 and #2211 and the main author is @jason01180118. The changes from me are

generate opcode from Refine rvp riscv/riscv-opcodes#409
add disassembler
fix some compilation warnings, names, and corner incorrect behavior

chihminchao · 2026-03-11T06:56:27Z

For some reason, the CI was stuck as building step
https://github.com/riscv-software-src/riscv-isa-sim/actions/runs/22936376083/job/66568524696#step:4:3543746

riscv/p_ext_macros.h

chihminchao · 2026-03-25T02:24:49Z

Update : 03/26/2026

add new instructions introduced by 0.20
fix the compilation warning reported by @arromanoff
all of them are caused by nclip-related ones in 9ed6e1c

chihminchao · 2026-03-25T15:48:23Z

update: 03/26/2026

forget to add rvp64 definition to makefile
add missing macro for zip series
make rv64p higher priority by overlap_list
fix opcode typo for wsla ext-p: fix typo riscv/riscv-opcodes#414

riscv/insns/psshar_dhs.h

riscv/riscv.mk.in

riscv/decode.h

riscv/insns/pabdu_b.h

riscv/insns/pabd_b.h

Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>

The complete set of instructions added for RV32 are: PSSHL.HS SSHL PSSHL.DHS PSSHL.DWS PSSHLR.HS SSHLR PSSHLR.DHS PSSHLR.DWS And for RV64: PSSHL.HS PSSHL.WS SHL PNCLIPP.B PNCLIPP.H PNCLIPP.W PSSHLR.HS PSSHLR.WS SHLR PNCLIPUP.B PNCLIPUP.H PNCLIPUP.W reference: https://www.jhauser.us/RISCV/ext-P/RVP-instrEncodings-020.pdf https://www.jhauser.us/RISCV/ext-P/RVP-baseInstrs-Sail-020.txt Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>

Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>

make rv64_p instructions higer priority Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>

Per the P-extension spec, any instruction that performs saturation must set the vxsat CSR to 1 when the result is clamped. 70 instructions were missing this write, addressed here in two ways: 1. Convert P_SAT, P_USAT, and P_USAT_FULL macros from pure expression macros to GCC statement expressions that detect when saturation occurs and write P.VU.vxsat. This automatically fixes ~42 instructions that use these macros (nclip/nclipi/nclipr/nclipri families, psati, psslai, pssh1sadd, pusati, sati, usati, ssh1sadd, sslai, and their packed/double-wide variants). 2. Add explicit vxsat writes to 22 instructions with inline saturation logic that bypasses the macros: - mulq/mulqr/pmulq/pmulqr: set vxsat on INT_MIN * INT_MIN overflow - psas/pssa cross variants: set vxsat from sat_add/sat_sub sat flag - pssha/psshar DW variants: set vxsat from ov overflow flag - pssha/psshar/ssha/sshar: set vxsat in sshamt >= BIT overflow path - pusati_dh/pusati_dw: set vxsat on unsigned range clamping Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>

…_INT128 Replace bare __int128 / unsigned __int128 in psshar_dhs.h and psshar_dws.h with the int128_t / uint128_t typedefs from fesvr/byteorder.h, and guard the entire riscv_insn_ext_p list in riscv.mk.in with $(if $(HAVE_INT128),...) matching the existing pattern for the V extension Signed-off-by: Chih-Min Chao <chihmin.chao@sifive.com>

chihminchao · 2026-04-08T03:07:27Z

Several change in this version

use a new macro to tell clip and sati. The saturation behavior is a little different
return the even register number rather than encoding field
mimic V/Q to check int128 support and use standard in128_t type
simplify abd related calculation
add missing vxsat update for some saturation instructions.

aswaterman · 2026-04-08T22:00:00Z

riscv/insn_template.h

 #include "internals.h"
 #include "specialize.h"
 #include "tracer.h"
+#include "p_ext_macros.h"


I think this is causing the CI failure.

Note that Spike CI tests that all commits are functional, so you will need to squash this change into the commit that removed p_ext_macros.h.

Ping me when the PR is ready to merge. Thanks @chihminchao!

arromanoff reviewed Mar 19, 2026

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chihminchao force-pushed the rvp-rv32-rv64 branch from f935bb4 to 91cc12d Compare March 25, 2026 02:21

chihminchao force-pushed the rvp-rv32-rv64 branch from 91cc12d to 7dffa63 Compare March 25, 2026 15:45