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Pull requests: riscv-software-src/riscv-isa-sim
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Fix execution when trigger/debug matched at interactive mode
#2269
opened Apr 7, 2026 by
Steven-Li-Xiaogang
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Fix incorrect mip.SEIP handling by adding hardware SEIP latch & correcting PLIC aliasing
#2218
opened Jan 21, 2026 by
rmkhurana28
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[Zvdot4a] Renaming Zvqdotq to Zvdot4a and vdotq to vdot4a
#2212
opened Jan 18, 2026 by
nibrunieAtSi5
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Draft
Implemented the ability to execute any postprocess provided by the plugin after each instruction
#2172
opened Dec 2, 2025 by
kseniadobrovolskaya
Contributor
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Support label-based sideband commands for printing register contents
#2024
opened Jul 2, 2025 by
maerhart
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ADD: a basic BTM N-trace spec compliant trace encoder model
#1824
opened Sep 30, 2024 by
iansseijelly
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Fix vleff: reduce VL if trigger fired on a later element.
#1818
opened Sep 26, 2024 by
NewPaulWalker
Contributor
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